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Title: Observable time windows: Verifying high-level synthesis results
Authors: Bergamaschi, R.A.
Raje, S.
Keywords: Algorithms
Computational linguistics
Computer simulation
High level languages
Systems analysis
High level synthesis
Implementation state
Observable time windows
Specification state
Computer hardware description languages
Issue Date: 1997
Citation: IEEE Design and Test of Computers, 14(2), 40-50
Abstract: Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
ISSN: 7407475
Appears in Collections:Articles

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