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- Publication1 st workshop on C3VP, 24 th international ACM Mobicom 2018(01-10-2018)
;Venkataraman, Hrishikesh ;Mysore, Raghavendra; Satyavolu, Surya - Publication3-D stochastic finite elements for thermal creep analysis of piping structures with spatial material inhomogeneities(01-09-2017)
;Appalanaidu, Y. ;Roy, AnindyaA stochastic finite element-based methodology is developed for creep damage assessment in pipings carrying high-temperature fluids. The material properties are assumed to be spatially randomly inhomogeneous and are modelled as 3-D non-Gaussian fields. A spectral-based approach for random field discretization that preserves exactly the non-Gaussian characteristics is used in developing the stochastic finite element model. The meshing used in random field discretization is distinct from FE meshing, depends on the correlation characteristics of the random fields and is computationally efficient. The methodology enables estimating the failure probability and the most likely regions of failure in a section of a circular pipe. - Publication3-Dimensional numerical modeling of geosynthetic-encased granular columns(01-06-2017)
;Mohapatra, Sunil Ranjan ;Rajagopal, K.Sharma, JitendraIn this paper, series of three-dimensional (3-d) numerical modeling of geosynthetic-encased granular columns were performed both in model and prototype scale using FLAC3D software to understand the lateral load carrying capacity of ordinary and geosynthetic encased granular columns (OGC and EGC). In the first part of the study, numerical modeling of direct shear tests were carried out. The soil in the direct shear box was reinforced with two different diameters of granular columns (50 mm and 100 mm) and three different patterns of arrangement (single, triangular and square) to study the effect of group confinement. The numerical simulations were carried out at four different confining pressures namely 15, 30, 45 and 75 kPa. From the numerical simulations it was observed that higher shear stresses are mobilized inside the granular column due to geosynthetic encasement and the magnitude of shear stress increases with increase in the normal pressure. It was found that the tensile forces in the geosynthetic encasement were mobilized both in circumferential and vertical directions, which helps in mobilizing additional confinement in the granular column. In the second part, the influence of the geosynthetic encasement of granular column treated soft ground was demonstrated through 3-dimensional slope stability analyses. - Publication3D massively parallel high throughput single cell electroporation(01-01-2018)
; ;Nagai, Moeto ;Wu, Ting H. ;Clemens, Daniel L. ;Lee, Bai Y. ;Wen, Ximiao ;Patananan, Alexander N. ;Teitell, Michael A.Chiou, Pei Y.Introduction of foreign macromolecules into single living cells with high transfection efficiency, high cell viability and high throughput are challenging task in cell biology and therapeutic research. Here we developed a 3D massively-parallel high throughput single-cell electroporation (MSEP) chip, which uniformly transfect single mammalian cells in parallel fashion with low applied voltages (3V~15V) and low signal (10KHz~10MHz) and achieved high delivery efficiency with high cell viability. This device have approximate 5000 holes (each hole diameter ~ 15µm) in parallel fashion on silicon substrate and electric field confined on top of each holes. When cells with cargo passes through each holes, electric field highly intense in each cells, resulting cell membrane deformation and create transient membrane pores to deliver exogenous cargo into cells. Our platform have ability to deliver molecules in 10 million cells/min by using 1 cm2 chip size. Using this MSEP device, we successfully deliver different sizes of dextran proteins, GFP plasmids into both adherent (HeLa) and non-adherent (THP-1) cells using different flow rates. This uniform single cell transfection with high efficiency and cell viability might be potentially application for single cell therapy, diagnostics and regenerative medicine purpose. - Publication400 Gbps PM-QPSK transmission for metro-DCI applications employing 20 gbaud transmitter(01-01-2018)
;Narayanan, Lakshmi ;Sobhanan, Aneesh; A PM-QPSK superchannel transmission is experimentally demonstrated for 400-Gbps data center interconnects, based on 20-GBd transmitter and coherent receiver technology, yielding a spectral efficiency of 4-b/s/Hz. - Publication5-Benzoyl triazole as new structural dimension in glycoconjugates(01-11-2018)
;Sahoo, Laxminarayan ;Kundu, Soumya ;Singhamahapatra, Anadi ;Jena, Naresh K. ;Nayak, Ganesh C.Sahoo, SatyanarayanIn recent years, 1,4-triazole rings are being widely used for the synthesis of carbohydrate derived biomimetics, due to their easy synthesis and wide range of functional group compatibility. These triazole rings lead to synthetic molecules with improved enzymatic stability, bioavailability, and structural diversity. In this present work, a benzoyl group has been introduced at the C-5 position of the triazole ring present in the synthetic glycoconjugates providing further structural diversity to the molecule. 5-Benzoyl 1,4-triazole ring containing glycoconjugates were synthesized using Cu(I) catalyzed [3 + 2] cycloaddition reaction of per-O-acetylated glycopyranosyl azide and phenyl acetylene followed by in situ electrophilic addition of benzoyl group to the Cu(I) coordinated triazole intermediate. The X-ray crystal structure of one of the 5-benzoyl 1,4-triazole linked glycoconjugate derived from D-xylose {1-N-(2,3,4-tri-O-acetyl-β-D-xylopyranosyl)-4-phenyl-5-benzoyl-1,2,3-triazole} showed unique pattern of intermolecular C–H…O interactions arranging the molecules in an anti-parallel orientation. The structure and morphology of the compounds were further explored using computational calculation and scanning electron microscopic (SEM) study which firmly established the uniqueness of 5-benzoyl 1,4-triazole linked glycoconjugates compared to that of 5-H 1,4-triazole linked derivative. - Publication80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory with No Added Process Complexity(01-03-2018)
;Jayaraman, Balaji ;Leu, Derek; ;Cestero, Alberto ;Yin, Ming ;Golz, John ;Tummuru, Rajesh Reddy ;Raghavan, Ramesh ;Moy, Dan ;Kempanna, Thejas ;Khan, Faraz ;Kirihata, ToshiakiIyer, Subramanian S.This paper describes the design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity. Charge trap transistors (CTTs) that exploit charge trapping and de-trapping behavior in high-K dielectric of 32-/22-nm Logic FETs are used as storage elements with logic-compatible programming voltages. A high-gain slew-sense amplifier (SA) is used to efficiently detect the threshold voltage difference (Δ VDIF) between the true and complement FETs in the twin cell. Design-assist techniques including multi-step programming with over-write protection and block write algorithm are used to enhance the programming efficiency without causing a dielectric breakdown. High-temperature stress results show a projected data retention of 10 years at 125 °C with a signal loss of <30% that is margined in while programming, by employing a sense margining logic in the SA. Scalability of CTT has been established by the first demonstration of CTT-based MTPM in 14-nm bulk FinFET technology with read cycle time of 40 ns at 0.7-V VDD. - PublicationA 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR(09-05-2018)
;Manivannan, SaravanaPavan, ShanthiThe high dynamic range of CTΔΣMs used in wireless receivers, needed to accommodate large out-of-band interferers, can be reduced by using a filter up front. Embedding the filter inside the modulator loop is more power efficient. Prior work has embedded a Tow-Thomas biquad inside the ADC. We show that using a Rauch filter instead yields higher out-of-band linearity (for the same power dissipation) due to the passive-RC filtering inherent in the Rauch structure. The theory is borne out by measurements from a 1 MHz bandwidth CTΔΣM with an embedded second-order Rauch filter, achieving 76 dB SNDR and 36 dBFS out-of-band IIP3 while consuming 2.2 mW in a 65 nm CMOS process1. - PublicationA 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 \mu m CMOS(01-08-2017)
;Mondal, ImonAn all-pass filter architecture that can be generalized to high orders, and can be realized using active circuits is proposed. Using this, a compact true-time-delay element with a widely tunable delay and a large delay-bandwidth product (DBW) is demonstrated. This is useful for beamforming and equalization in the lower GHz range where the use of LC or transmission line-based solutions to realize large delays is infeasible. Coarse tuning of delay is realized by changing the filter's order while keeping the bandwidth constant and fine tuning is implemented by changing the filter's bandwidth utilizing the delay-bandwidth tradeoff. A test chip fabricated in 0.13 \mu \text{m} CMOS process demonstrates a delay tuning range of 250 ps-1.7-ns, over a bandwidth of 2 GHz, while maintaining a magnitude deviation of ±0.7 dB. The filter achieves a DBW of 3.4 and a delay per unit area of 5.8 \mathrm {ns/mm^{2}}. The filter has a worst case noise figure of 23 dB, and -40 dB intermodulation (IM3) distortion for 37 mVppd inputs. The chip occupies an active area of 0.6 mm2, and dissipates 112 mW-364 mW of power between its minimum and maximum delay settings. Computed radiation pattern with four antennas spaced \mathrm {\lambda -{fmax}}/2 apart shows ±90° beam steering off broadside. - PublicationA 2.5-GHz CMOS Full-Duplex Front-End for Asymmetric Data Networks(01-10-2018)
;Kumar, AbhishekElectrical balance-based full-duplex front-end allows high power operation but has strong tradeoff between Tx and Rx insertion loss. In this paper, we present a capacitive bridge-based duplexer for full-duplex operation with tunable Tx/Rx insertion loss to improve link budget in an asymmetric data network. Theoretical analysis is done to show that capacitive bridge-based duplexer can be better than hybrid transformer in CMOS process. Capacitive bridge architecture is suitable for insertion loss tunability and this tunability gives an additional advantage of increasing the range of allowed antenna impedance for the given balance network. The fully integrated duplexer with receiver is implemented in a 130-nm CMOS process, and is capable of handling Tx power of upto +16dBm at antenna. The prototype chip demonstrates tunable Tx/Rx insertion loss achieving an overall receiver noise figure of 5.7-7.5dB and a Tx insertion loss of 3.9-5.6dB. Self-interference cancellation of >50dB is measured for 20-MHz RF bandwidth in 2.4-2.6-GHz frequency range. - PublicationA 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver(01-05-2017)
; ;Shu, Guanghua ;Nandwana, Romesh Kumar ;Talegaonkar, Mrunmay ;Elkholy, Ahmed ;Anand, Tejasvi ;Choi, Woo SeokHanumolu, Pavan KumarDesign techniques to improve energy efficiency of serial link transceivers are presented. Power consumption is reduced by using: 1) low-power clock generation, recovery, and distribution schemes; 2) charge-based circuits to implement analog front-end and samplers/flip-flops; and 3) a partially segmented voltage-mode (VM) output driver. An LC-oscillator based digital phase-locked loop (PLL) is used to generate a low jitter clock that is shared between the transmitter (Tx) and receiver (Rx). The clock recovery unit uses a local ring-oscillator based PLL to reduce the number of phase interpolators and the amount of high-frequency clock distribution. Charge-based samplers that were shown to operate with limited return-to-zero voltage swings and consume only dynamic power are modified to provide non-return-to-zero outputs and used extensively in the deserializer and Rx front-end circuits. A partially segmented VM output driver with embedded 2-tap de-emphasis is proposed to reduce power consumption of pre-drivers. Fabricated in a 65 nm CMOS process, the 14 Gb/s transceiver prototype employs aforementioned techniques and achieves an energy efficiency of 2.8 mW/Gb/s. The Tx achieves a phase margin of 0.36 UI (BER = 10-12) at the end of an 11 dB loss channel with an energy efficiency of 0.89 mW/Gb/s. The Rx recovers clock with 1.8 psrms long term absolute jitter at BER < 10-12 and achieves an energy efficiency of 1.69 mW/Gb/s. The LC-oscillator based digital PLL achieves an integrated jitter of 0.605 psrms with an energy efficiency of 0.5 mW/GHz at 7 GHz output frequency. - PublicationA 27.2GHz bipolar LC-VCO using class-C biasing to maximize achievable Fosc in 130nm BiCMOS(26-04-2018)
;Thakkar, Arpan ;Theertham, Srinivas ;Mirajkar, Peeyoosh ;Goyal, Jagdish ChandA BJT based cross-coupled pair limits the maximum achievable oscillation frequency of LC-VCOs due to high parasitic capacitance in mature Si/SiGe technologies. In this work, class-C biasing is exploited to reduce cross-coupled pair parasitics, helping to enhance oscillation frequency without compromising phase noise performance. A design methodology is suggested to optimize cross-coupled pair parasitics with better phase noise performance. A dual-core architecture helps to achieve further phase noise improvement. The VCO is designed and fabricated in a 130nm BiCMOS technology using a bipolar cross-coupled pair. It achieves a maximum oscillation frequency of 27.2GHz and exhibits a measured phase noise performance of -110.7dBc/Hz @ 1MHz offset from the carrier, with an FoM of 181dBc/Hz. - PublicationA 3.9-4.5GHz class-C VCO with accurate current injection based on capacitive feedback(19-12-2017)
;Thakkar, Arpan ;Theertham, Srinivas ;Mirajkar, Peeyoosh ;Goyal, Jagdish ChandA class-C VCO with dual negative feedback architecture is proposed to break the trade-off between amplitude stability of oscillation and bias current flicker noise. Inherent dynamic biasing of this architecture maximizes available voltage swing and provides robust current control without any additional circuits. To inject current exactly at the peak of oscillation, a capacitive feedback technique is proposed which improves phase noise performance further by compensating current injection delay caused due to cross-coupled pair parasitics. This VCO has been implemented in 130nm BiCMOS technology using BJT based cross-coupled pair. It exhibits phase noise performance of -131dBc/Hz @ 1MHz offset when running at 3.9GHz. It exhibits a 14% tuning range, and presents an FoM of 184dBc/Hz. - PublicationA 4-port inductor based compact dual-core VCO with improved phase noise performance(01-12-2017)
;Thakkar, Arpan ;Bhatia, Apoorva ;Sharma, Vikram ;Theertham, SrinivasUtilizing the concept of impedance scaling, dualcore LC-VCO helps to meet stringent phase noise requirement at the cost of higher power and higher area. A 4-port inductor with dual tap is proposed for dual-core LC-VCO architecture which reduces power consumption for the given phase noise performance or improves phase noise performance for given power consumption. 4-port inductor has lesser effect of current crowding and hence it has better quality factor which leads to improvement in phase noise performance. Significant area reduction is also obtained due to single 4-port inductor as against two 2-port inductors with higher separation to avoid mutual coupling in traditional dual core LC-VCO. Traditional dual-core VCO and 4-port inductor based dualcore VCO have been implemented in 130 nm BiCMOS technology to compare the phase noise performance. 4-port based dual core VCO demonstrates phase noise improvement of 3 dB at 1 MHz offset when running at 21.4 GHz. - PublicationA 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS(01-09-2017)
;Talegaonkar, Mrunmay ;Anand, Tejasvi ;Elkholy, Ahmed ;Elshazly, Amr ;Nandwana, Romesh Kumar; ;Young, Brian ;Choi, Woo SeokHanumolu, Pavan KumarA highly digital two-stage fractional- N phase-locked loop (PLL) architecture utilizing a first-order 1-bit ΔΣ frequency-to-digital converter (FDC) is proposed and implemented in a 65nm CMOS process. Performance of the first-order 1-bit ΔΣ FDC is improved by using a phase interpolator-based fractional divider that reduces phase quantizer input span and by using a multiplying delay-locked loop that increases its oversampling ratio. We also describe an analogy between a time-to-digital converter (TDC) and a ΔΣ FDC followed by an accumulator that allows us to leverage the TDC-based PLL analysis techniques to study the impact of ΔΣ FDC characteristics on ΔΣ FDC-based fractional- N PLL (FDCPLL) performance. Utilizing proposed techniques, a prototype PLL achieves 1 MHz bandwidth, -101.6 dBc/Hz in-band phase noise, and 1.22 ps rms (1 kHz-40 MHz) jitter while generating 5.031GHz output from 31.25MHz reference clock input. For the same output frequency, the stand-alone second-stage fractional- N FDCPLL achieves 1MHz bandwidth, -106.1dBc/Hz in-band phase noise, and 403 fs rms jitter with a 500MHz reference clock input. The two-stage PLL consumes 10.1mW power from a 1V supply, out of which 7.1 mW is consumed by the second-stage FDCPLL. - PublicationA 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD(01-12-2017)
;Shibata, Hajime ;Kozlov, Victor ;Ji, Zexi ;Ganesan, Asha ;Zhu, Haiyang ;Paterson, Donald ;Zhao, Jialin ;Patil, SharvilPavan, ShanthiAn oversampled continuous-time (CT) pipeline ADC clocked at 9 GHz achieving 1.125-GHz bandwidth and -164 dBFS/Hz average small-signal noise density is presented. In contrast to traditional discrete-time (DT) pipeline ADCs, the system processes the signals in CT form throughout all the pipeline stages and thus sampling-induced artifacts such as aliasing and high-peak ADC driving current are mitigated. Despite the oversampled nature of the ADC, its digitization bandwidth is on par with that of traditional non-interleaved DT pipeline ADCs since CT signal processing is not constrained by settling time requirements. The ADC was fabricated in a 28-nm CMOS process technology and consumes 2.3 W. - PublicationA basal ganglia model of freezing of gait in parkinson’s disease(01-01-2018)
;Muralidharan, Vignesh ;Balasubramani, Pragathi Priyadharsini; Moustafa, Ahmed A.Freezing of gait (FOG) is a mysterious clinical phenomenon seen in Parkinson’s disease (PD) patients, a neurodegenerative disorder of the basal ganglia (BG), where there is cessation of locomotion under specific contexts. These contexts could include motor initiation, i.e., when starting movement, passing through narrow passages and corridors, while making a turn and as they are about to reach a destination. We have developed computational models of the BG which explains the freezing behavior seen in PD. The model uses reinforcement learning framework, incorporating Actor–Critic architecture, to aid learning of a virtual subject to navigate through these specific contexts. The model captures the velocity changes (slowing down) seen in PD freezers upon encountering a doorway, turns, and under the influence of cognitive load compared to PD non-freezers and healthy controls. The model throws interesting predictions about the pathology of freezing suggesting that dopamine, a key neurochemical deficient in PD, might not be the only reason for the occurrences of such freeze episodes. Other neuromodulators which are involved in action exploration and risk sensitivity influence these motor arrests. Finally, we have incorporated a network model of the BG to understand the network level parameters which influence contextual motor freezing. - PublicationA biologically plausible architecture of the striatum to solve context-dependent reinforcement learning tasks(21-06-2017)
;Shivkumar, Sabyasachi ;Muralidharan, VigneshBasal ganglia circuit is an important subcortical system of the brain thought to be responsible for reward-based learning. Striatum, the largest nucleus of the basal ganglia, serves as an input port that maps cortical information. Microanatomical studies show that the striatum is a mosaic of specialized input-output structures called striosomes and regions of the surrounding matrix called the matrisomes. We have developed a computational model of the striatum using layered self-organizing maps to capture the center-surround structure seen experimentally and explain its functional significance. We believe that these structural components could build representations of state and action spaces in different environments. The striatummodel is then integrated with other components of basal ganglia, making it capable of solving reinforcement learning tasks. We have proposed a biologically plausible mechanism of action-based learning where the striosome biases the matrisome activity toward a preferred action. Several studies indicate that the striatum is critical in solving context dependent problems. We build on this hypothesis and the proposed model exploits the modularity of the striatum to efficiently solve such tasks. - PublicationA Bottom-Up Saliency Estimation Approach for Neonatal Retinal Images(01-01-2018)
;Shankaranarayana, Sharath M. ;Ram, Keerthi ;Vinekar, Anand; Retinopathy of Prematurity (ROP) is a potentially blinding disease occurring primarily in prematurely born neonates. Staging or classification of ROP into various stages is mainly dependant on the presence of ridge or demarcation line and its distance with respect to optic disc. Thus, computer aided diagnosis of ROP requires method to automatically detect the ridge. To this end, a new bottom up saliency estimation method for neonatal retinal images is proposed. The method consists of first obtaining a depth map of neonatal retinal image via an image restoration scheme based on a physical model. The obtain depth is then converted to a saliency map. Then the image is further processed to even out illumination and contrast variations and the border artifacts. Next, two additional saliency maps are estimated from the processed image using gradient and appearance cues. The obtained saliency maps are then fused by pixel-wise multiplication and addition operators. The obtained final saliency map facilitates the detection of demarcation line and is qualitatively shown to be more suitable for neonatal retinal images compared to the state of the art saliency estimation techniques. This method could thus serve as tool for improved and faster diagnosis. Additionally, we also explore the usefulness of saliency maps for the task of classification of ROP into four stages.