Publication6

Nanopores have been used for myriad applications ranging from water desalination, gas separation, fluidic circuits, DNA sequencing, and preconcentration of ions. In all of these applications noise is an important factor during signal measurement. Noisy signals disrupt the exact measuring signal in almost all of these applications. In this paper, we rationalize whether current oscillations should be classified only as noise or the physical disturbance in ionic charges has some other meaning. We infer that the physical disturbance in ionic charges and the current oscillations are not noise but can be chaos. Chaos is present in the system due to depletion of the ions, created by nonequilibrium anharmonic distribution in the electrostatic potential. In other words, multiple electric potential wells are observed in the nanoporous system. The multiple electric potential wells leads to bi-directional hopping of ions as the ions transport through the pore. The bi-directional hopping results in current oscillations. This paper suggests that chaos exists from a deterministic perspective and that there is no stochastic element leading to current oscillations. We prove this case by considering a simple oscillator model involving the electrostatic and dissipative forces in order to model ionic current. We observed current oscillations even in the absence of a stochastic noise force. Hence, we state that current oscillations in nanopores can be due to chaos as well and not necessarily due to noise. Furthermore, the color associated with the chaotic spectrum is not brown but pink, with 1/f type dynamics similar to the 1/f type pink noise presented by theorists and experimentalists. However, the 1/f type pink chaos exists due to deterministic current oscillations and not due to a stochastic fluctuating noise force.

Cost-effective counter electrode (CE) with high electrocatalytic performance is very much essential for the wide application of dye-sensitized solar cells (DSSC). The 1D-2D carbon heterostructure (Pt/GR@CNT) with low platinum (Pt) loading has been synthesized by a facile in situ microwave-assisted polyol-reduction method. The excellent electrocatalytic activity as well as photovoltaic performance was achieved due to the combination of 2D graphene nanoribbons (GR) and 1D multi-walled carbon nanotubes (CNT) with high catalytically active Pt nanoparticles. Microwave-assisted longitudinal unzipping of few outer layers of CNTs along with co-reduction of Pt nanoparticles is an effective method to create electrochemically active defective edge sites, which have a crucial role in enhancing electrochemical performance. Synergistic effect of ultra-fine Pt nanoparticles, partially unzipped graphene nanoribbons and inner core tubes of CNTs modulates the power conversion efficiency of solar cell to 5.57% ± 0.03 as compared with 4.73% ± 0.13 of CNTs. Pt/GR@CNT CE even with low Pt loading of 14 μg cm−2 showcases equivalent performance with that of pure Pt counter electrode. [Figure not available: see fulltext.]

3-E (Energy, Exergy, and Environment) analysis of Pressurized Pulverized Combined Cycle (PPCC) SubCritical (SubC) and SuperCritical (SupC) power plants of net capacity 400 MWe using High Ash (HA) Indian coal under Indian ambient conditions is performed to assess the potential of PPCC power plant for electricity generation in Indian energy sector. The study also includes the comparative performance of the plant using an imported Low Ash (LA) coal and a parametric study is performed to understand the effect of various parameters affecting the energy and exergy efficiencies of the PPCC plant. It is found that the plant energy efficiency of PPCC SubC and SupC plants using HA coal are 42.44% and 43.46%, respectively. The exergy efficiency of the same plant using HA coal are 38.94% and 39.87%, respectively. The energy balance shows that the maximum energy loss is observed in cooling water (24%) followed by loss in stack (22%). The exergy balance shows that the maximum exergy destruction in combustor (32%) followed by stack (7%). The environmental analysis reveals that the CO2, NOx, and SOx emissions are 426, 3.54, and 3.20 g/kWh, respectively.

In this paperwe propose a method to find collision free path fromthe starting position to the target in the 2D grid via a labeled isotonic array P system which enables only 4-directional movements of the robot by excluding diagonal moves. The proposed grammatical model finds a collision free path in polynomial time.

An ultra-low-voltage 5 GHz differential low noise amplifier (LNA) is designed and simulated in a UMC 130nm CMOS process. It employs the Darlington structure for improved fT in sub-Threshold region, and operates from a supply voltage of just 0.6V while consuming a total current of 1.4mA. The cascode-less LNA implements capacitive feedback neutralization for improved stability. The LNA exhibits a peak voltage gain of 25dB and minimum noise figure (NF) of 1.8dB. It is input matched to a differential resistance of 100Ω with input reflection coefficient S11 < -10dB over 5.1-5.9 GHz, and the input third-order intercept (IIP3) is +10dBm.

Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phase-locked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. Specifically, their deterministic jitter (DJ), which is proportional to the loop update rate becomes prohibitively large at low reference clock frequencies. We propose a scrambling TDC (STDC) to improve DJ performance and a cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage to achieve low random jitter in a power efficient manner. Fabricated in a 90 nm CMOS process, the prototype frequency synthesizer consumes 4.76 mW power from a 1.0 V supply and generates 160 MHz and 2.56 GHz output clocks from a 1.25 MHz crystal reference frequency. The long-term absolute jitter of the 160 MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter are 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.

A driver amplifier suitable for integration with an 18 bit 500 kS/s successive approximation register analog-to-digital converter (ADC) is reported. It accepts single-ended or fully differential inputs. The driver consumes 12.5 mW from a 5 V supply, has a -115 dB (-120 dB) total harmonic distortion for 8 Vppd output at 1 kHz (10 kHz), a 240 ns settling time to 0.01% accuracy for a 2 Vppd output step, and an input-referred noise of 11.1 nV/√Hz. Simulated 18 bit settling time is 900 ns, and σ input-referred offset is 1.2 mV. This is one of the first reported 18 bit CMOS ADC driver amplifiers, and its performance is comparable to that of the state-of-the-art parts in other processes.

We present a wideband single-bit CTΔΣM that uses a 2× time-interleaved quantizer and FIR DAC. Time interleaving reduces power dissipation and regeneration errors of the FIR DAC when compared to a full rate implementation. Fabricated in a low leakage 65nm CMOS, the prototype modulator operates at 6 GS/s and achieves 67.6/76 dB SNDR/DR in a 60 MHz bandwidth while consuming 13.3 mW. The FoM is 56.5 fJ/conv-step.

CTDSMs operated in the incremental mode can achieve sample-by-sample conversion in a power efficient manner, while relaxing the requirements of the buffer driving the ADC. This work gives simple expressions for quantization and thermal noise of an incremental CTDSM. These are used to design a two channel incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel. The ADC, designed in a 180nm CMOS process, achieves 85.1dB SNDR while consuming 55uW/channel from a 1.8 V supply.

A method for the detection of location and size of a crack in simple structures using a nanocomposite sensor is discussed. In the present study, a piezoelectric/single walled carbon nanotube composite sensor is modeled on piezoelectric principle. The effective piezoelectric and dielectric properties of the composite at 0.2 volume fraction loading of single walled carbon nanotubes is determined by micromechanical analysis. By means of these effective properties a piezoelectric sensor has been modeled. The transfer function and bode response of this sensor is investigated. The sensor is fixed at a location on a cantilever beam and the response of the sensor with respect to the size and location of the crack is modeled. The analytical values are compared with ANSYS. It is assumed that there is no slippage between the sensor and the beam surface. The sensor behavior with respect to dynamic loading conditions is also studied. It is ascertained that the relative position of the sensor with respect to crack is crucial and determines the sensitivity of the sensor to detect a crack. Results are presented in the form of voltage output from the sensor at different crack locations and at varying lengths of the crack.

Many industrial applications require high-resolution ADCs whose low-frequency performance is important. CTDSMs are attractive due to their implicit antialiasing and resistive inputs. However, their low-frequency precision is degraded by flicker noise. The loop filter of such modulators is usually realized using active-RC techniques, and the CTDSMs' 1/f noise is mostly due to the input stage of the 1st OTA. Using large input devices to reduce 1/f noise greatly increases area occupied by the input stage, and degrades linearity due to the increased parasitic capacitance at the OTA virtual ground.

Serial link transceivers that can operate across a wide range of data rates offer flexibility and rapid realization of single-chip multi-standard solutions. The ability to independently control the data rate of each lane in a multi-lane transceiver with fine granularity is also valuable [1,2]. The implementation of such transceivers would require analog front-ends and clocking circuits that can operate over a wide range of frequencies. As a result, compared to transceivers that are optimized to operate at one single data rate, flexible-rate transceivers are power and area hungry [1]. Because a single PLL cannot generate clocks across the entire interface operating range, [1,2] use multiple LC tanks, carefully optimized waveform shaping circuits, power hungry clock distribution, and complex frequency planning methods.

Flame spread over an array of fuel sheets of finite width size has been modeled and numerically investigated for opposed, low convective flows in microgravity. As opposed to the previous studies based on 2D models, steady flame spread rates were observed for all separation distances up to the separation distance of flame extinction. The flame spread rate increased with decrease in separation distance up to a point where it was maximum, further reduction in separation distance, reduced the flame spread rate. The flammability map as a function of separation distance was also obtained for different fuel widths. While the extinction map qualitatively matches with the flammability map obtained from the 2D model, the flame extinguished at higher oxygen levels with the decrease in fuel width due to radiation heat losses.

Chip based digital isolators are being developed for higher speed and higher isolation capabilities [1, 2]. These make use of various coupling mechanisms such as capacitive coupling [3] and transformer coupling [4]. A limitation of these technologies is that they need to maintain a low separation (distance through insulation DTI<30μm) through high quality insulators (oxides, polyamides) in order to achieve data rate and isolation performance [2]. These require expensive special process development and special packaging techniques to meet reinforced isolation recommended by IEC 60747-5-5 and VDE 0884-10. Other high-speed die-to-die communication techniques implemented using millimeter-wave and optical solutions are expensive and not designed for isolation. In this work, an isolation technique is proposed where two standard 180nm CMOS dies placed side by side with DTI of more than 500μm, and co-packaged using regular planar MCM flow with package mold compound being the isolation material, achieve asynchronous bidirectional link with >24kV surge isolation capability and greater than 500Mb/s at 175pJ/b. Channel gain is maximized using resonance. Gain is decoupled from channel bandwidth by resetting the channel state variables. This helps in enhancing data rate well beyond what is implied by the bandwidth.

Nonlinear oscillations lie at the heart of numerous complex systems. Impulsive forcing arises naturally in many scenarios, and we endeavour to study nonlinear oscillators subject to such forcing. We model these kicked oscillatory systems as a piecewise smooth dynamical system, whereby their dynamics can be investigated. We investigate the problem of pattern formation in a turbulent combustion system and apply this formalism with the aim of explaining the observed dynamics. We identify that the transition of this system from low amplitude chaotic oscillations to large amplitude periodic oscillations is the result of a discontinuity induced bifurcation. Further, we provide an explanation for the occurrence of intermittent oscillations in the system.

In this brief, we consider quantum-dot cellular automata (QCA) realization of the discrete Hadamard transform (DHT). An analysis of a full-parallel solution based on efficient multibit addition in QCA is first presented. We show that this leads to large area as well as delay. We then propose a bit-serial pipelined architecture for QCA-based DHT. The proposed architecture is based on a new one-bit adder-subtractor requiring only six majority gates and a feedback latch that requires only one majority gate and limited wiring. The approach leads to a reduction in area-delay-cycle product of 74% and 91% (over a full-parallel solution) for wordlengths of 4 and 8, respectively. Results of simulations in QCADesigner are also presented.

A silicon vertex detector (SVD) for the Belle-II experiment comprises four layers of double-sided silicon strip detectors (DSSDs), assembled in a ladder-like structure. Each ladder module of the outermost SVD layer has four rectangular and one trapezoidal DSSDs supported by two carbon-fiber ribs. In order to achieve a good signal-to-noise ratio and minimize material budget, a novel chip-on-sensor “Origami” method has been employed for the three rectangular sensors that are sandwiched between the backward rectangular and forward (slanted) trapezoidal sensors. This paper describes the bonding procedures developed for making electrical connections between sensors and signal fan-out flex circuits (i.e., pitch adapters), and between pitch adapters and readout chips as well as the results in terms of the achieved bonding quality and pull force.

This paper presents a 'Computer Aided Design (CAD)' model for energy efficient design of offshore structures. In the CAD model preliminary dimensions and geometric details of an offshore structure (i.e. semi-submersible) are optimized to achieve a favorable range of motion to reduce the energy consumed by the 'Dynamic Position System (DPS)'. The presented model allows the designer to select the configuration satisfying the user requirements and integration of Computer Aided Design (CAD) and Computational Fluid Dynamics (CFD). The integration of CAD with CFD computes a hydrodynamically and energy efficient hull form. Our results show that the implementation of the present model results into an design that can serve the user specified requirements with less cost and energy consumption.

A coaxial twin counter-rotating air swirl prefilming injector with necessary optical access, is developed to visualize and quantify its internal fluid dynamics. This research injector consists of a simplex nozzle arranged at the center of two coaxial counter-rotating radial air flow swirlers, and two transparent coaxial tubes are attached, one each to the primary and secondary air swirl paths. Spray from the simplex nozzle is swirled by the primary air and impinges on the inner tube - the prefilmer, undergoes filming, and convects to the tube tip to form a liquid rim, which is sheared by the counter-rotating swirl into finer droplets. Stage-wise phase Doppler particle analyzer measurements indicate the final spray to be much finer than the simplex nozzle spray after undergoing the above processes. Time resolved laser induced fluorescence (TR-LIF) imaging techniques are applied to visualize the wall filming and primary atomization inside the injector. The simplex nozzle spray velocity under the influence of air swirl flow is measured using stereo-particle image velocimetry. The precessing vortex core from the primary swirl imparts a precessing motion to the simplex spray, which in turn induces a non-uniform filming on the prefilmer. The droplet impingement on the prefilmer leads to splashing and crater formation on the surface. The crater size distribution is obtained and compared to the droplet size of the injector spray before impingement. The film thickness variation on the prefilmer surface and the rim thickness are estimated from planar LIF experiments along with a long distance microscope. The thickness of the liquid rim is identified as a major factor in determining the final droplet size at the injector exit. These are correlated to SMD at the injector exit at different air flow rates.