K Sridharan

In this chapter, we present key aspects of the CNTFET technology. As indicated earlier, carbon nanotubes have bandgaps that are dependent on the diameter of the tubes [1]. Also, the bandgap turns out to be a measure of the threshold voltage of the CNTFET.

This paper presents two efficient ternary SRAM designs appropriate for several transistor-based technologies. The first design is based on the cycle operator in ternary logic while the second is a buffer-based design that employs the positive and negative ternary inverters. Both the designs consume low power in comparison to existing standard ternary inverter-based SRAM designs. Further, the read and write delay for the proposed designs are much lower than the corresponding ones for existing designs. Detailed analyses of the proposed circuits are presented. Extensive HSpice simulations (and comparisons) using a Carbon Nanotube Field Effect Transistor library are reported. The proposed designs also have noise margins comparable to existing designs.

This research has studied digital design in the context of emerging nanotechnologies. In particular, we have studied the problem of designing arithmetic circuits in Carbon Nanotube Field Effect Transistor technology. We have presented a number of theoretical results on ternary logic. The results facilitate reduction of transistor count for various circuits. We now list the contributions and touch upon extensions to the work.

Dynamic obstacles present a challenge for navigation of mobile robots. Estimation of the velocity of dynamic obstacles helps in collision avoidance. In this paper, we propose a hardware-efficient approach for velocity estimation that is appropriate for FPGA-driven mobile robots. The proposed approach is based on a novel approximate radix-4 CORDIC algorithm with low latency. The new CORDIC requires at most four iterations for convergence and has very low area requirement. Using the proposed CORDIC, we present an iterative method for velocity estimation. The velocity estimation scheme achieves roughly 87% reduction in slice-delay product compared to a direct algebraic approach (that uses multipliers). Experiments with an FPGA-based robot are reported.

We have discussed the design of CNTFET-based adders in the earlier chapters. In this chapter, we present the design of a ternary multiplier. We note that the design of a single-digit multiplier itself is non-trivial in the ternary setting.

Map-making is a challenging task when the environment is unknown and the collected information is local. This paper presents the design of a hardware architecture for sensor-based map construction in a planar environment. In particular, the map is a Voronoi diagram of the environment. The Voronoi construction is based on a control law. Features of the proposed architecture are absence of arithmetic operations expensive in digital hardware and a planning algorithm for completing the map. Also, the implementation of control-law uses look-up tables and reuse of CORDIC module to avoid matrix multiplications. A highly area-efficient FPGA implementation of the architecture is also reported. Experiments with an FPGA-based robot confirm the effectiveness of the proposed approach.

Tangent graph based data structure has been readily used in motion planning for mobile robots and robot manipulators. The complexity of the tangent graph grows exponentially as the robot's configuration space increases in dimension. The ability to construct larger number of tangents at high speed thus becomes crucial to facilitate dynamic motion planning where on-line avoidance is necessary. In this paper, we present efficient schemes for construction of tangent graphs for an environment consisting of both non-convex and convex obstacles. The proposed technique for tangent graph construction is based on a gradient computation approach that encompasses binary search, logarithmic approximation, and half-plane computation modules. The modules were ported to Very Large Scale Integration (VLSI) using commercial tools. Synthesis results show that each module has a latency of only 7.2 ns and a total chip area of about 7K NAND gates, thus demonstrating that the proposed techniques are highly appropriate for tangent graph computations in real-time applications. © 2005 Elsevier B.V. All rights reserved.

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this paper is on the analysis of reliability of combinational logic circuits at the transistor level with the goal of application to these technologies. To this end, we present an approach for the calculation of the output probabilities for basic logic primitives that comprise a combinational circuit. Using the output probabilities, a computationally efficient algorithm (based on Hadamard product) is presented to calculate the reliability. As an application of the proposed algorithm, we analyze the reliability of adder circuits composed of carbon nanotube FETs considering fabrication-level parameters. We then investigate adder characteristics that lead to high reliability independent of the technology. In particular, we propose a new multibit adder termed hybrid adder offering high reliability with low area requirement for various transistor-based emerging technologies. Detailed simulation results are presented to support the analysis.

Mobile robots are used for search and rescue purposes in emergency informatics. The robots typically carry a vision system to gather information about the environment and pass on to remotely located rescue teams. When the robot moves, in view of the uneven nature of the terrain, the camera is subjected to vibrations and as a result, the transmitted videos tend to be unclear. Further, real-time data collection and processing are critical for quick action by rescue personnel. In this paper, we explore a robust and high-performance approach for video stabilization. In particular, we develop a systolic array for interest point detection and description, key phases in the speeded-up robust features (SURF) approach for finding point correspondences between two images of a scene. The systolic array is then used as part of a pipelined architecture for video stabilization. The entire architecture is ported on to a field-programmable gate array (FPGA) for real-time video stabilization on a mobile robot. Experiments with the FPGA-driven robot in our laboratory and institute corridors validate the efficacy of the proposed strategy.

In previous chapters, we have developed CNTFET-based designs for specific operations such as addition and multiplication. We provided various “thumb-rules” for reducing the transistor count. In this chapter, we attempt to answer the following question: Can the process of synthesis be automated ? We provide an outline of an automatic synthesis procedure and also touch upon coding in Python. A study of the synthesis problem is also pursued in [1].