Anjan Chakravorty

An existing water distribution network (WDN) may need to be expanded by adding a sub-network for the newly developed areas. The size of the problem becomes larger when the stochastic nature of domestic demands, optimal design and layouts, control, and operation of various hydraulic components are considered. In this study, the single-port Thevenin theorem used in electrical circuits is applied to reduce a large WDN with its equivalent network consisting of a single source and a single pipe. The equivalent network is then attached to a sub-network for focused analysis. The accuracy and robustness of the proposed network reduction procedure are investigated on realistic WDNs for various sub-network demands using steady and extended period simulations. A simplified approach is also presented to achieve the same objective but constrained by the level of accuracy. Hydraulic engineers can use the proposed methodology as an efficient network reduction tool.

In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is presented. The proposed modeling technique takes as inputs the dimensions of emitter fingers, shallow and deep trench isolations, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are validated against 3D TCAD simulations of multifinger bipolar transistors with and without trench isolations. Geometry scalability of the model is also demonstrated.

Detailed formulations for DC and AC emitter current crowding are presented in view of developing an extended π-equivalent circuit (EC) model to accurately predict the lateral non-quasi-static effects in silicon germanium heterojunction bipolar transistors. Under negligible DC current crowding, the EC reduces to a simple π-model. The implementation-suitable versions of the models are also developed. Compared to state-of-the-art model formulations, the extended π-model shows better accuracy in predicting device simulated data. If desired, the high level of accuracy obtained by the extended π-model can be traded with the required extra simulation time due to one extra node.

In this article, the effect of charge partitioning in a silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor on its nonlinearity model is investigated. It is found that the prediction of the third-order intermodulation distortion (IM3) depends on the model equivalent circuit (EC) and appropriate charge assignments at various nodes therein. The investigation is carried out using a highly accurate static model of LDMOS along with a couple of different charge-partitioning schemes in order to single out their effects on the nonlinearity model behavior. We observe that charge partitioning in a more flexible EC framework yields an improved IM3 prediction when compared with the TCAD simulated results.

In this paper, we present extensive random telegraph signal (RTS) noise characterization in advanced SiGe:C heterojunction bipolar transistors. In frequency domain, in addition to 1/f noise, generation-recombination (G-R) mechanisms are observed at low base bias in the base noise. Their existence is confirmed by RTS noise measurements in time domain. The RTS amplitude evolves rather slowly with bias, indicating their mechanism to have originated in peripheral locations. In the collector side, on the onset of high-current effects, distinct RTS noise is observed that possibly originates from the traps in the trench regions. Extraction of time constants from RTS noise and their bias dependence are presented that provides estimation of trap location within the device structure.

In this paper, we present extensive random telegraph signal (RTS) noise characterization in SiGe heterojunction bipolar transistors. RTS noise, observed at the base, originates at the emitter periphery while at the collector side distinct RTS noise is observed at high-injection that originates from the traps in the shallow trench regions. Time constants extracted from RTS during aging tests allow understanding of trap dynamics and new defect formation within the device structure. This paper provides the first demonstration of RTS measurements during accelerated aging tests to study and understand generation of defects under bias stress in SiGe HBTs operating at the limit of their safe-operating area.

This paper investigates alternative topologies of silicon germanium heterojunction bipolar transistors designed and fabricated in the state-of-the-art BiCMOS process from STMicroelectronics for improved safe-operating characteristics. Electrical and thermal behaviors of various structures are analyzed and compared, along with a detailed discussion on drawbacks and advantages. The test structures under study are different in terms of emitter-finger layouts as well as the metal stacks in the back-end-of-line. It is observed that the multifinger transistor structures having nonuniform finger lengths with wider area enclosed by the deep trench and higher metallization stacks yield an improved thermal behavior. Therefore, the safe-operating area of multifinger transistors can be extended without degrading the RF performances.

A modified physics-based two-section model is proposed to accurately capture the lateral non-quasi-static effect in SiGe HBTs. A methodology is proposed to include the DC emitter current crowding effect in the existing two-section model framework. The proposed two-section model is implemented in Verilog-A. The large-signal transient and the small-signal AC simulations are carried out and the results are compared with the numerical device simulation data. The proposed model is observed to perform better than the existing two-section model and the state-of-the-art standard model from the perspectives of small-signal frequency-domain characteristics and large-signal transients.

In this paper, we develop a correlated noise model for bipolar transistors from an accurate nonquasi-static model. The proposed noise model includes the signal delay through base-collector space-charge region and is implemented using four extra nodes. We also present a simplified version of the same model that requires only two extra nodes. A further simplified version that uses only one extra node is found to be identical with a state-of-the-art correlated noise model. When compared with the device simulation data, our proposed models show improved accuracy compared with the existing state-of-the-art noise models.

In this paper for the first time, a frequency independent equivalent circuit model is proposed for series stacked inductors having variable width and space (taper) across their turns. The proposed model accounts for the increase in mutual inductance between the stacked spirals due to taper. Also, the proximity effect losses with tapered top and bottom spirals of the series stack is accurately modeled. Finally, the inter-layer capacitance between the stacked spirals which dictates the self-resonant-frequency of the series inductor is calculated across different values of taper. EM simulations and measurements show excellent correlation with model simulations across different layouts with different values of taper thereby demonstrating the scalability of the proposed model.