Now showing 1 - 10 of 19
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    Effect of Charge Partitioning on IM3 Prediction in SOI-LDMOS Transistors
    (01-02-2020)
    Gupta, Shubham
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    Nikhil, Krishnannadar Savithry
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    In this article, the effect of charge partitioning in a silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor on its nonlinearity model is investigated. It is found that the prediction of the third-order intermodulation distortion (IM3) depends on the model equivalent circuit (EC) and appropriate charge assignments at various nodes therein. The investigation is carried out using a highly accurate static model of LDMOS along with a couple of different charge-partitioning schemes in order to single out their effects on the nonlinearity model behavior. We observe that charge partitioning in a more flexible EC framework yields an improved IM3 prediction when compared with the TCAD simulated results.
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    An improved quasi-saturation and charge model for SOI-LDMOS transistors
    (01-01-2015)
    Prasad, Nitin
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    Sarangapani, Prasad
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    Nikhil, Krishnan Nadar Savithry
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    In this paper, we report an accurate quasi-saturation model and a nodal charge model for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (SOI-LDMOS) transistors. First, a model of a 2-D SOI resistor under velocity saturation is developed, which is subsequently incorporated into the drift region of an LDMOS transistor to predict the quasi-saturation effect. The gate-voltage dependence of the quasi-saturation current is also modeled. Second, we propose a new nodal charge model to describe the dynamic behavior of the device. Comparisons of modeling results with device simulation data show that the proposed model is accurate over a wide range of bias. Scalability of the model with respect to the length of the drift region under the field oxide is also demonstrated. Finally, the model is validated under device self-heating conditions and by comparing it with the experimental data.
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    Compact Modeling of Static and Transient Effects of Buffer Traps in GaN HEMTs
    (01-03-2022)
    Shanbhag, Ajay
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    Sruthi, M. P.
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    We propose a physics-based analytical model that accurately captures the effects of buffer traps on dc characteristics of gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs). The model is then semi-analytically extended to additionally include the transient behavior. Analytical formulations for the shift in the threshold voltage ${(}{V}_{\text {OFF}}{)}$ and two-dimensional electron gas (2-DEG) density due to the presence of buffer traps in the steady state are presented. In pulsed operation, technology computer-aided design (TCAD) simulations indicate that a time-dependent negative potential (NP) is developed under the gate, resulting in a modified ${V}_{\text {OFF}}$ and current collapse (CC). An expression for the modified ${V}_{\text {off}}$ helps capture the pulsed current-voltage characteristics. The model captures the dependence of bias, time, temperature, trap concentration, capture cross section area, and activation energy of traps on the steady-state and transient characteristics. The model is implemented in Verilog-A in an existing compact model framework using a diode and RC sub-circuit and validated using measured data and TCAD simulations. The modeling results are in excellent agreement with the experimental data and TCAD simulations. Since the model is physics-based, it requires fewer number of parameters compared to that in the existing models.
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    Publication
    SOI-LDMOS Transistors with optimized partial n+ buried layer for improved performance in power amplifier applications
    (01-11-2018)
    Nikhil, Krishnannadar Savithry
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    In this paper, for the first time, we demonstrate the improvement in power capability and safe operating area of silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors for power amplifier applications by the introduction of a partial n+ buried layer (PNBL). The power capability of a transistor can be evaluated by Pmax/A, which is the maximum power per unit area that can be delivered by the transistor and is an important parameter for power amplifiers. Pmax is dependent on the snapback voltage (Vsb,QS), OFF-state breakdown voltage (Vbd, OFF), and maximum current (Imax) in the quasi-saturation regime of an LDMOS transistor. Increase of Pmax/A by the introduction of a PNBL in the SOI-LDMOS transistors is reported in this paper. The effects of variation of the length, thickness, and doping concentration of the PNBL on Vsb,QS and Pmax/A are analyzed in detail. It is shown that by optimizing the doping and length of the PNBL layer, the maximum power output from the transistor can be made significantly higher than that of a conventional device without PNBL. A procedure to design the optimized structure is also presented.
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    Analytical Model for Gate Capacitance and Threshold Voltage in Fin-Shaped GaN HEMTs
    (01-09-2021)
    Sruthi, M. P.
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    Shanbhag, Ajay
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    Fin-shaped tri-gate structure is an alternative way to achieve positive threshold voltage shift in gallium nitride (GaN)-based high electron mobility transistors (HEMTs). This results from the combined effect of top-gate and side-gate electric fields. In this work, side-gate capacitance of fin-shaped high electron mobility transistor (fin-HEMT) is estimated using conformal mapping technique. Subsequently, a model is developed to estimate the threshold voltage of the device by incorporating this side-gate capacitance in the existing threshold formulation. This model can be included in any existing compact model framework of HEMTs to predict the threshold voltage for fin-shaped devices. The proposed model, being completely physics-based and scalable, is useful to circuit engineers for optimal design.
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    Cross-coupled Self-Heating and Consequent Reliability Issues in GaN-Si Hetero-integration: Thermal Keep-Out-Zone Quantified
    (01-01-2023)
    Sruthi, M. P.
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    Zaman Mamun, M. Asaduz
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    Nair, Deleep R.
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    Alam, Muhammad Ashraful
    Three-dimensional (3D) hetero-integration (HI) allows Moore's law to be extended by integrating multiple materials and device technologies onto a single platform, thereby increasing the device density, performance, and functionality. 3D- HI unlocks new circuit applications and capabilities, for instance, by combining III- V devices with high-density and low-cost silicon digital control circuits. However, typically the design processes of such HI systems focus on process or performance considerations without accounting for cross-coupled reliability. We assert that the 3D-HI design would be suboptimal unless we explicitly account for the reliability issues emerging from, for example, the cross-coupled self-heating effects (SHE) that can pose severe reliability challenges of such hetero-integrated circuits. As such, we (i) propose a thermal model to predict the maximum temperature (T_max) attained by Si devices that are heterogeneously integrated with a hot GaN power transistor, (ii) derive an analytical model to define thermal keep-out-zone (T-KOZ) between different devices, and (iii) demonstrate how reliability issues in Si transistor, such as negative bias temperature instability (NBTI), hot carrier injection (HCI) and interconnect electromigration (EM) can be mitigated by carefully selecting the substrate material and implementing forced cooling. The method is generic and can be tailored for any arbitrary combination of technologies.
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    Modeling of SOI-LDMOS transistor including impact ionization, snapback, and self-heating
    (01-11-2011)
    Radhakrishna, Ujwal
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    A physics-based compact model for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor transistors including impact ionization, subsequent snapback (SB), and self-heating (SH) is presented. It is observed that the SB effect is caused by the turn-on of the associated parasitic bipolar transistor. The model includes the effect of device SH using resistive thermal networks for each region. Comparisons of modeling results with device simulation data show that, over a wide range of bias voltages, the model exhibits excellent accuracy without any convergence problem. © 2011 IEEE.
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    Compact modeling of SOI-LDMOS including quasi-saturation effect
    (01-12-2009)
    Lekshmi, T.
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    Mittal, Amit Kumar
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    This paper presents a physics-based compact dc model for high voltage silicon on insulator lateral double diffused MOS (SOI-LDMOS) transistor, assuming uniform doping for the channel. It uses MM20 model for the channel and drift region under the thin gate oxide, and proposes a new model for the drift region under the field oxide. This model shows that the current at higher gate voltages in SOI-LDMOS, is limited by the velocity saturation in the drift region under the field oxide, which determines the device behavior in the quasi-saturation region. The model exhibits high level of accuracy over wide bias ranges. ©2009 IEEE.
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    An accurate method to extract thermal resistance of GaN-on-Si HEMTs
    (22-05-2023)
    Shanbhag, Ajay
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    Khade, Ramdas P.
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    Sarkar, Sujan
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    Sruthi, M. P.
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    Nair, Deleep
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    An accurate method to extract the thermal resistance ( R T H ) of GaN-on-Si high electron mobility transistors (HEMTs) is proposed. It is shown that by pulsing the substrate, instead of drain or gate as done in the existing methods, one can significantly reduce the effect of traps on the extraction process. To demonstrate this, HEMTs are fabricated on two wafers, similar in all respects except that one has a carbon-doped buffer and the other does not. We obtain the same value of RTH for the two wafers using the proposed method, while the values are significantly different using the method based on drain pulsing. The extracted RTH is also used in a compact model to demonstrate the accuracy of the proposed method.
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    Prediction of IMD behaviour in LDMOS transistor amplifiers using a physics-based large signal compact model
    (18-10-2017)
    Gupta, Shubham
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    Nikhil, Krishnannadar Savithry
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    In this paper, intermodulation distortion (IMD) analysis is carried out for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor using a physics-based large signal model implemented in Verilog-A. The model is found to predict the static and dynamic characteristics accurately along with the higher order derivatives of transconductance and capacitances in all regions of operations. A power amplifier (PA) is designed both within the TCAD mixed-mode simulation framework and circuit simulator using the Verilog-A compact model. One-tone and two-tone analysis are carried out for the PAs designed in TCAD and circuit simulators. It is found that the Verilog-A compact model can accurately predict the existence of double IMD sweetspots for class AB operation when compared with the TCAD results. Also for the output power, power gain and power added efficiency, the model predictions are in agreement with those of the TCAD simulation data.