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Nandita DasGupta
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Nandita DasGupta
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Nandita DasGupta
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DasGupta, N.
Basu, Nandita
Basu, N.
Dasgupta, N.
DasGupta, Nandita
Gupta, Nandita Das
Dasgupta, Nandita
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26 results
Now showing 1 - 10 of 26
- PublicationEffect of Charge Partitioning on IM3 Prediction in SOI-LDMOS Transistors(01-02-2020)
;Gupta, Shubham ;Nikhil, Krishnannadar Savithry; ; In this article, the effect of charge partitioning in a silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor on its nonlinearity model is investigated. It is found that the prediction of the third-order intermodulation distortion (IM3) depends on the model equivalent circuit (EC) and appropriate charge assignments at various nodes therein. The investigation is carried out using a highly accurate static model of LDMOS along with a couple of different charge-partitioning schemes in order to single out their effects on the nonlinearity model behavior. We observe that charge partitioning in a more flexible EC framework yields an improved IM3 prediction when compared with the TCAD simulated results. - PublicationCompact Modeling of Static and Transient Effects of Buffer Traps in GaN HEMTs(01-03-2022)
;Shanbhag, Ajay ;Sruthi, M. P.; ; We propose a physics-based analytical model that accurately captures the effects of buffer traps on dc characteristics of gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs). The model is then semi-analytically extended to additionally include the transient behavior. Analytical formulations for the shift in the threshold voltage ${(}{V}_{\text {OFF}}{)}$ and two-dimensional electron gas (2-DEG) density due to the presence of buffer traps in the steady state are presented. In pulsed operation, technology computer-aided design (TCAD) simulations indicate that a time-dependent negative potential (NP) is developed under the gate, resulting in a modified ${V}_{\text {OFF}}$ and current collapse (CC). An expression for the modified ${V}_{\text {off}}$ helps capture the pulsed current-voltage characteristics. The model captures the dependence of bias, time, temperature, trap concentration, capture cross section area, and activation energy of traps on the steady-state and transient characteristics. The model is implemented in Verilog-A in an existing compact model framework using a diode and RC sub-circuit and validated using measured data and TCAD simulations. The modeling results are in excellent agreement with the experimental data and TCAD simulations. Since the model is physics-based, it requires fewer number of parameters compared to that in the existing models. - PublicationNear-Ideal Subthreshold Swing in InAlN/GaN Schottky Gate High Electron Mobility Transistor Using Carbon-Doped GaN Buffer(01-08-2022)
;Sarkar, Sujan ;Khade, Ramdas P. ;Shanbhag, Ajay; — This work presents a comparative study of the subthreshold swing (SS) in InAlN/GaN-based high electron mobility transistor (HEMT), with and without carbon doping in the buffer layer. It is observed that devices with carbon-doped (C-doped) buffer exhibit near-ideal SS of close to 60-mV/decade over a wide range of drain voltage for both up and downsweep. The C-doped buffer layer reduces the OFF-state drain leakage current and increases the drain current ON/OFF ratio. TCAD simulation of the vertical electric field under the gate shows that the sample with a C-doped buffer layer has a much lower value of the peak electric field at the drain side edge of the gate, resulting in lower reverse-biased gate leakage current and smaller SS compared to that of the undoped buffer. Moreover, the junction capacitance at the interface of the unintentionally doped GaN (UID:GAN) and the C-doped buffer layer, in series with the depletion capacitance, reduces the overall capacitance, which further improves the SS in the C-doped wafer. - PublicationLow temperature and high pressure oxidized Al2O3as gate dielectric for AlInN/GaN MIS-HEMTs(01-09-2020)
;Kanaga, Srikanth ;Dutta, Gourab ;Kushwah, Bhuvnesh; Low temperature (LT) and high pressure oxidized (HPO) Al2O3 is investigated as a gate dielectric for AlInN/GaN MIS-HEMTs. The time and temperature of the oxidation process was optimized for best performance. X-ray photoelectron spectroscopic (XPS) studies confirmed the near complete oxidation of Al to form Al2O3. MIS-HEMTs with 7 nm thick LT-HPO Al2O3 showed six orders reduction in gate leakage current and five orders improvement in ID,ON/ID,OFF ratio compared to the reference HEMT. Also, these MIS-HEMTs proved to be significantly better than HEMTs in terms of maximum drain current, subthreshold slope and off-state breakdown voltage. Reliability studies under constant voltage stress conditions show that the threshold voltage variation is within acceptable limits. Interface trap charges were estimated with the help of dynamic capacitance dispersion technique. The improved current collapse in MIS-HEMTs over HEMTs indicates the good quality of the interface between the dielectric and barrier layer. - PublicationSuppression of Impact Ionization by Carbon Doping in the GaN Buffer Layer in InAlN/GaN-Based High Electron Mobility Transistors(01-08-2023)
;Sarkar, Sujan ;Khade, Ramdas P.; Herein, the impact ionization in InAlN/GaN-based high electron mobility transistors (HEMTs) is studied for the first time. It is shown that the carbon doping in the GaN buffer layer can suppress impact ionization by reducing the electric field at the drain side gate edge. For comparison, two wafers are taken. In one wafer (D1), the GaN buffer layer is unintentionally doped, and in another wafer (D2), the buffer layer is carbon doped with a doping concentration of (Formula presented.) at a distance of 500 nm from the InAlN–GaN interface. The impact ionization is probed from the bell-shaped nature of the IG – VGS characteristics. The bell-shaped nature is observed in D1 for the drain-to-source voltage (VDS) (Formula presented.) 6 V, whereas it is absent in D2. Floating source measurements confirm the occurrence of impact ionization in D1. At a lower temperature (−60 °C), the impact ionization rate of D1 increases even though there is no sign of impact ionization in D2. A technology computer-aided design simulation shows that the peak electric field at the drain side gate edge of D2 is lower than that of D1. - PublicationAnalytical Model for Gate Capacitance and Threshold Voltage in Fin-Shaped GaN HEMTs(01-09-2021)
;Sruthi, M. P. ;Shanbhag, Ajay; ; Fin-shaped tri-gate structure is an alternative way to achieve positive threshold voltage shift in gallium nitride (GaN)-based high electron mobility transistors (HEMTs). This results from the combined effect of top-gate and side-gate electric fields. In this work, side-gate capacitance of fin-shaped high electron mobility transistor (fin-HEMT) is estimated using conformal mapping technique. Subsequently, a model is developed to estimate the threshold voltage of the device by incorporating this side-gate capacitance in the existing threshold formulation. This model can be included in any existing compact model framework of HEMTs to predict the threshold voltage for fin-shaped devices. The proposed model, being completely physics-based and scalable, is useful to circuit engineers for optimal design. - PublicationDeep-Level Traps in AlGaN/GaN- And AlInN/GaN-Based HEMTs with Different Buffer Doping Technologies(01-06-2020)
;Raja, P. Vigneshwara ;Bouslama, Mohamed ;Sarkar, Sujan ;Pandurang, Khade Ramdas ;Nallatamby, Jean Christophe; Deep-level traps in AlGaN/GaN- and AlInN/GaN-based HEMTs with different buffer doping technologies are identified by drain current transient spectroscopy (DCTS) and low-frequency (LF) output admittance ( {Y}_{{22}} ) dispersion techniques. TCAD simulations are also carried out to determine the spatial location and type of traps. The DCTS and LF {Y}_{{22}} measurements on Al0.25Ga0.75N/GaN HEMT (Fe-doped buffer) reveal a single electron trap at {E}_{C} - {0.47} eV. On the other hand, an electron trap at {E}_{C} - (0.53-0.59) eV and a deep hole trap at {E}_{V} + {0.82} eV are detected in Al0.845In0.155N/AlN/GaN HEMT with unintentionally doped (UID) buffer, while a slow detrapping behavior is noticed at {E}_{C} - {0.6} eV in Al0.83In0.17N/AlN/GaN HEMT with C-doped buffer. The DCTS and LF {Y}_{{22}} measurements yield nearly the same trap signatures, indicating the reliability of the trap characterization techniques used in this article. The simulated LF {Y}_{{22}} characteristics show that all these traps are acceptor-like states located in the buffer layer. The identified trap parameters in various buffers may be helpful to improve the crystalline quality of the epitaxial buffer layers. - PublicationCross-coupled Self-Heating and Consequent Reliability Issues in GaN-Si Hetero-integration: Thermal Keep-Out-Zone Quantified(01-01-2023)
;Sruthi, M. P. ;Zaman Mamun, M. Asaduz ;Nair, Deleep R.; ; ; Alam, Muhammad AshrafulThree-dimensional (3D) hetero-integration (HI) allows Moore's law to be extended by integrating multiple materials and device technologies onto a single platform, thereby increasing the device density, performance, and functionality. 3D- HI unlocks new circuit applications and capabilities, for instance, by combining III- V devices with high-density and low-cost silicon digital control circuits. However, typically the design processes of such HI systems focus on process or performance considerations without accounting for cross-coupled reliability. We assert that the 3D-HI design would be suboptimal unless we explicitly account for the reliability issues emerging from, for example, the cross-coupled self-heating effects (SHE) that can pose severe reliability challenges of such hetero-integrated circuits. As such, we (i) propose a thermal model to predict the maximum temperature (T_max) attained by Si devices that are heterogeneously integrated with a hot GaN power transistor, (ii) derive an analytical model to define thermal keep-out-zone (T-KOZ) between different devices, and (iii) demonstrate how reliability issues in Si transistor, such as negative bias temperature instability (NBTI), hot carrier injection (HCI) and interconnect electromigration (EM) can be mitigated by carefully selecting the substrate material and implementing forced cooling. The method is generic and can be tailored for any arbitrary combination of technologies. - PublicationGate Current Partitioning Model for Schottky Gate GaN HEMTs(01-01-2021)
;Debnath, Ankur ;Sarkar, Sujan ;Pandurang, Khade Ramdas; A gate current partition scheme for Schottky gate GaN-based high-electron-mobility transistors (HEMTs) using a charge-based approach is proposed. Analytical expressions for gate-to-drain and gate-to-source components of Fowler-Nordheim tunneling (FNT), Poole-Frenkel emission (PFE), thermionic emission (TE), and defect assisted tunneling (DAT) currents are derived. This current partition model is implemented in Verilog-A and validated with experimental results for a wide range of gate and drain bias. The model also passes the symmetry test. - PublicationCharge-Based Compact Model of Gate Leakage Current for AlInN/GaN and AlGaN/GaN HEMTs(01-03-2020)
;Debnath, Ankur; The gate leakage current is analytically modeled for AlInN/GaN and AlGaN/GaN high-electron mobility transistor (HEMT) devices using a charge-based approach. Four different current mechanisms, namely Fowler-Nordheim tunneling (FNT), Poole-Frenkel emission (PFE), thermionic emission (TE), and defect-assisted tunneling (DAT) are considered. FNT and PFE are two dominant mechanisms in the reverse bias region, while TE and DAT are significant in forward and near zero gate bias regions, respectively. This model is implemented in Verilog-A and validated by comparison with experimental data for both AlInN/GaN and AlGaN/GaN HEMTs. It is shown that the model is able to capture the effects of Al molar fraction, barrier thickness, and temperature on gate leakage current over a wide range of gate and drain voltages.
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