Nandita DasGupta

Dielectric materials with permittivity higher than that of SiO2 are becoming increasingly important in ULSI technology as they allow the physical thickness of the gate dielectric to be higher while maintaining the same gate capacitance as in a conventional MOS process. This reduces the gate leakage current, which has become a serious problem in modern MOSFETs with a gate oxide thickness less than 4 nm. In this paper we present the characteristics of MTOS capacitors with a Ta2O5/SiO2 stacked dielectric layer and compare the results with MOS capacitors having an equivalent dielectric thickness. It is shown that the leakage current is considerably smaller and the breakdown voltage significantly higher in the MTOS devices.

MOS capacitors with ultrathin (≅1.2 nm) oxide grown by different techniques have been fabricated on Strained Si/Relaxed SiGe/n-Si substrates with linearly graded SiGe. These techniques involve thermal oxidation, chemical oxidation and both followed by anodic oxidation. Significant improvement in interface states has been obtained when oxidation was followed by anodic oxidation. The leakage currents and reliability characteristics have also shown great improvement. Band gap offsets extracted using a simple and novel technique are found to match well with expected values. © 2007 IEEE.

We have succeeded in growing a stable and ever eluding p-type (Li, Ni): ZnO using a codoping technique. Pulsed laser deposited (PLD) films grown in a small window of oxygen partial pressures (10-3 - 10-2 mbar) showed room temperature carrier density ∼ 2.1 × 10-17 cm-3̇ Ohmic properties of Ni/Au contact on p-ZnO films were studied using LTLM method. Efforts have also been made to grow different nano forms of ZnO and study their optical properties for various device application prospects. © 2010 IEEE.

MIS capacitors on nitrided and non-nitrided Ge substrates with HfO 2 as the dielectric have been studied. Effective oxide thickness is found to be reduced after nitridation. Significant improvements in the electrical characteristics are observed for the devices fabricated on nitrided substrates. The value of density of interface states is found to be lower for nitrided device when compared to non-nitrided device. Leakage current is drastically reduced for the nitrided device. The Breakdown field strength is improved from 11.3 MV/cm for the non-nitrided device to 15.89 MV/cm for the nitrided device. © 2007 IEEE.

The modal transition loss between straight and 90° bend rib waveguide structures on Silicon-on-Insulator platform have been optimized with the simulated results using Finite Element Method (FEM) and Beam Propagation Method (BPM). We have studied different asymmetric configurations to minimize the radius of curvature of bend waveguide. The simulation results shows that a 90° bend waveguide is possible with a bending radius as low as 800 μm keeping the loss budget to ∼ 1 dB. © 2008 IEEE.

The Asymmetric Gate Dielectric (AGD) MOSFET, where the equivalent dielectric thickness is higher at the source end than at the drain end, is studied with the help of simulations. A study of the properties of this device shows that, compared to the symmetric structure, the channel electric-field is larger at the source end resulting in higher carrier velocity and smaller at the drain end resulting in reduced short channel effects. The AGD devices show lesser Drain Induced Barrier Lowering and higher voltage gain compared to conventional devices, which should be useful for both digital and analog applications. The device structure has also been optimized for best performance. © 2007 IEEE.

The etching of single crystal silicon in ethylenediamine-pyrocatechol-water solutions (EDP) has been studied as a function of the composition of the etching solution. The solution with a constant composition of 7.5ml of ethylenediamine (with 6g of pyrazine per liter) and 1.2g of pyrocatechol is used, and the water content is varied from 0ml to 4ml. Etch rate dependence on the active etching area is examined using three mask patterns having significantly different areas. It has been observed that etch rate depends significantly on the feature size in the solutions with higher water concentration and is almost independent of the area when the water content is 1ml and below. Surface morphology was the other important criteria considered while optimizing the solution. It is found that the hillocks formation on surface is dependent on the etchant composition. Hillock density has been measured by etching the samples in different compositions to a constant depth of 45μm. It is found to be high when the water content is above 2ml and also when the amount of water is reduced below 0.5ml. Minimal Hillock density is obtained when the water content is 0.5ml. The optimized EDP solution containing 0.5ml of water results in an etch rate of 44μm/hr, independent of feature size and also good surface finish with hillock density less than ∼103/cm2.

Rapid Thermal Oxidation (RTO) of AlGaN barrier has been employed to reduce the gate leakage current in AlGaN/GaN High Electron Mobility Transistors. Current Voltage (I - V) and Capacitance Voltage (C - V) characteristics of Schottky Barrier diodes and Metal Oxide Semiconductor diodes are compared. At room temperature, reduction in gate leakage current over an order of magnitude in reverse bias and four orders of magnitude in forward bias is achieved upon oxidation. While the gate current reduces upon RTO, gate capacitance does not change indicating gate control over the channel is not compromised. I - V and C - V characterization have been carried out at different temperatures to get more insight into the device operation. Copyright © Materials Research Society 2014.

Three-dimensional (3D) hetero-integration (HI) allows Moore's law to be extended by integrating multiple materials and device technologies onto a single platform, thereby increasing the device density, performance, and functionality. 3D- HI unlocks new circuit applications and capabilities, for instance, by combining III- V devices with high-density and low-cost silicon digital control circuits. However, typically the design processes of such HI systems focus on process or performance considerations without accounting for cross-coupled reliability. We assert that the 3D-HI design would be suboptimal unless we explicitly account for the reliability issues emerging from, for example, the cross-coupled self-heating effects (SHE) that can pose severe reliability challenges of such hetero-integrated circuits. As such, we (i) propose a thermal model to predict the maximum temperature (T_max) attained by Si devices that are heterogeneously integrated with a hot GaN power transistor, (ii) derive an analytical model to define thermal keep-out-zone (T-KOZ) between different devices, and (iii) demonstrate how reliability issues in Si transistor, such as negative bias temperature instability (NBTI), hot carrier injection (HCI) and interconnect electromigration (EM) can be mitigated by carefully selecting the substrate material and implementing forced cooling. The method is generic and can be tailored for any arbitrary combination of technologies.

Realisation of low-cost and reliable packaging techniques to couple the optical fibre with the photodetector has become a critical area of research today. In the present work we have developed a simple technique to automatically align the fibre with the detector by micromachining the InP substrate (used for fabricating the p-i-n detector) and using the resulting V-groove for accurate positioning of the fibre. A masking material has been deposited on the back surface of the wafer and patterned by photolithography to open an window exactly aligned to the p-i-n detector realised on the top surface. InP has been etched anisotropically through this window. This has resulted in a V-groove through which the fibre can be inserted and held in position. Three different etch mask materials viz. Ti, Cr and SiN have been tried and their effects on the shape of the v-groove have been compared. Two different etch solutions have been used to etch InP. It has been found that while the choice of the etching solution determines the angle of the v-groove as well as the surface finish, the mask material dictates the amount of undercut. Ti as the mask material has been found to give the best results.