Shreepad Karmalkar

Prior work on Silicon Carbide (SiC) power devices has been silent on the exact procedure to be employed for designing the Floating Field Rings (FFRs) meant for raising avalanche breakdown voltage of these devices. On the other hand, prior procedures for designing FFRs in Si devices do not work for kV range breakdown associated with SiC devices, and employ 10’s of μm long rings. We propose a systematic procedure for deriving the number and spacing of the FFRs of any ring length required for achieving an arbitrary breakdown voltage. The procedure can be adapted to implement any one of the ring spacing strategies, namely - constant, decreasing or increasing as one moves outward from the main junction. The procedure is demonstrated for the linearly increasing ring spacing case using TCAD simulations, considering 1.7–5.5 kV 4H-Silicon Carbide devices and a 700 V Si device reported in literature. The FFR structures resulting from our procedure are found to have a total length which is 24.5–75% of that published in literature, and breakdown voltage which is more than 92% of the plane parallel value.

Prior work has shown that the OFF-state breakdown voltage, VBR, of AlGaN/GaN high electron mobility transistors (HEMTs) can be raised by just extending the drain end of the gate as a field plate (FP) or a high-k passivation over the AlGaN layer. However, the two techniques have not been compared, and the VBR for which their effectiveness was demonstrated was ≥120 V. High-k passivation avoids the lithography involved in realizing a FP, and the VBR of practical devices can go down to a few 10's of volts. Hence the present work compares the effectiveness of these techniques by TCAD simulations and establishes the following. At VBR of few 10's of Volts, the high-k passivation is much less effective than the FP, e.g. for a device with VBR = 28 V, a 0.7 μm long FP over 0.105 μm thick SiN doubles the VBR to 56 V, whereas even a 0.5 μm thick HfO2 passivation (εr = 20) has almost no effect on VBR. However, such differences between the two techniques reduce progressively as VBR is raised. The differences vanish for VBR ≥ 100 V, for which both techniques can improve the VBR by ≥ 2.5 times. Although focused primarily on breakdown, our work gives quick calculations showing that the high-k passivation has 5 – 10 % higher gate-drain capacitance than the gate-connected FP.

This paper concerns superjunctions which employ oxide layers for isolating n- and p-pillars and in terminating the device. In our earlier work, we pointed out that oxide fixed charges significantly reduce the breakdown voltage of such devices. In this paper, we discuss various techniques in compensating the effects of oxide fixed charge so as to design such a device having the minimum specific on-resistance for a given breakdown voltage. The techniques include doping modification and reduction in the widths of terminating pillars and nonconducting pillars in the ON-state. We also analyze the relative contributions of oxide fixed charges and doping-related charge imbalance to breakdown reduction to highlight the significance of oxide fixed charges. © 2008 IEEE.

A novel HEMT configuration based on the RESURF technique is proposed for very high voltage power switching applications. It employs a p-n junction below the 2-DEG channel and two field plates, one extending from the gate and the other from the drain, to distribute the electric field over the gate to drain separation. 2-D simulations indicate a breakdown voltage > 1 KV at on-resistance of ∼1 mΩ-cm2 (neglecting contact resistances) for the device.

This paper provides more insight into the operation of the Charge Sheet Superjunction (CSSJ) proposed recently, whose specific on-resistance for a given breakdown voltage is even lower than that of a Superjunction (SJ). It is shown how the SJ and the CSSJ both evolve from a simple Γ-shaped p+-n junction in which the heavily doped region surrounds the lightly doped region; the peak field in such a 2-D junction is less than that in a plane junction. The phenomena underlying the I-V and C-V characteristics of the CSSJ MOSFET are clarified with the help of charge and potential simulations. A simple analytical model is developed for the drain-source capacitance of the CSSJ MOSFET; the model is shown to apply to SJ MOSFET as well. It is argued that the insulator charges providing the charge sheet essential for CSSJ operation will not present the same reliability problems as those due to trapped charge in the gate insulator of small-signal MOSFETs; this is because the insulator field distribution in a CSSJ differs significantly from that in a small-signal MOSFET. The insight provided in this paper should build a strong motivation for the practical implementation of the new structure. © 2008 IEEE.