Vinita Vasudevan

This paper presents a technique for the modification and optimisation of the one-dimensional full search (IDFS) motion estimation algorithm. The modified version of the IDFS algorithm has desirable properties for efficient hardware implementation. The spatial redundancy between the motion vectors of the macroblocks within a frame is exploited for the purpose of optimisation. The performance of the proposed technique is competitive, as compared to the more popular hierarchical three step search (TSS) method. The speed of the proposed technique, when implemented in hardware, is higher than the TSS method. The results of an implementation in an EPLD, targeted for real time operation, are given.

Approximate circuit design has gained significance in recent years targeting error-tolerant applications. In the literature, there have been several attempts at optimizing the number of approximate bits of each approximate adder in a system for a given accuracy constraint. For computational efficiency, the error models used in these routines are simple expressions obtained using regression or by assuming inputs or the error is uniformly distributed. In this article, we first demonstrate that for many approximate adders, these assumptions lead to an inaccurate prediction of error statistics for multi-level circuits. We show that mean error and mean square error can be computed accurately if static probabilities of adders at all stages are taken into account. Therefore, in a system with a certain type of approximate adder, any optimization framework needs to take into account not just the functionality of the adder but also its position in the circuit, functionality of its parents, and the number of approximate bits in the parent blocks. We propose a method to derive parameterized error models for various types of approximate adders. We incorporate these models within an optimization framework and demonstrate that the noise power is computed accurately.

One of the device models used for bipolar junction transistors (BJTs) in circuit simulators like SPICE is the Gummel-Poon model. Gummel-Poon model is an extension of Ebers-Moll model and includes second order effects. Gummel-Poon model defines 19 direct current (dc) and 21 alternating current (ac) parameters for BJT. In this context, all the Gummel-Poon model DC parameters are extracted for the BJT for a particular process. An optimized analysis is proposed for the extraction of the parameters modeling the base resistance of the BJT.

The use of quadratic gate delay models and arrival times results in improved accuracies for a parameterized block-based statistical static timing analysis (SSTA). However, the computational complexity is significantly higher. As an alternative to this, we propose a canonical model based on skew-normal random variables (SN model). This model is derived from the quadratic canonical models and can consider the skewness in the gate delay distribution as well as the nonlinearity of the MAX operation. Based on conditional expectations, we derive the analytical expressions for the moments of the MAX operator and the tightness probability that can be used along with the SN canonical models. The computational complexity for both timing and criticality analysis is comparable with SSTA using linear models. There is a two to three orders of magnitude improvement in the run time as compared with the quadratic models. Results on ISCAS benchmarks show that the SN models have a lower variance error than the quadratic model, but the error in the third moment is comparable with that of the semiquadratic model.

Artificial neural networks (ANNs) are increasingly being used for a variety of machine learning problems. However, increased density of interconnections in ANNs leads to high computational and power requirements. One way to reduce the power is to reduce the number of interconnections which can be achieved using least absolute shrinkage and selection operator (LASSO) techniques. In this brief, we propose an alternative smoothing function to LASSO regularization and an incremental pruning algorithm on feedforward ANNs with an aim of achieving maximally sparse networks with minimal performance degradation. We compare the results obtained using the proposed smoothing function with the existing smoothing functions. Further, we also evaluate the performance of the proposed incremental pruning algorithm.

A commonly used approach to compute the error rate at the primary outputs (POs) of a circuit is to compare the fault-free and faulty copies of the circuit using XOR gates. This model results in poor accuracies with nonsampling-based methods for reliability estimation. An alternative is to use a single copy of the circuit with a four-valued representation for each net corresponding to the correct and incorrect signals. One problem in this formulation is the accurate propagation of associated probabilities. We use the framework of Bayesian inference (BI) to address this issue. We derive the conditional probability distribution (CPD) corresponding to the four-valued signals and find the output error rate using various approximate BI techniques. With our formulation, we demonstrate that the output error rate scales with the gate error probabilities. It is guaranteed to be zero when the gate error probability is zero, provided approximate BI algorithms based on sum-product belief propagation (BP) are used. Although inaccuracies increase at very low gate error probabilities, it is able to capture the relative reliability of outputs with respect to each other. We also propose a new method for finding the overall circuit error rate as the partition function for a fixed state of POs. This method provides a significant improvement in accuracy when compared with the existing method using OR gates.

CAD tools developed for routing analog circuits have to give special consideration for the quality of the routes developed, owing to the high sensitivity of these circuits to small changes in the layout geometry. Cost based path-finding algorithms that find globally optimal solutions are thus best suited for implementing routing in analog circuits. In this paper, we propose a modification to the line expansion algorithm used previously, that results in significant savings in time and memory consumed.

Deep Neural Networks (DNNs) are increasingly being used in a variety of applications. However, DNNs have huge computational and memory requirements. One way to reduce these requirements is to sparsify DNNs by using smoothed LASSO (Least Absolute Shrinkage and Selection Operator) functions. In this paper, we show that irrespective of error profile, the sparsity values obtained using various smoothed LASSO functions are similar, provided the maximum error of these functions with respect to the LASSO function is the same. We also propose a layer-wise DNN pruning algorithm, where the layers are pruned based on their individual allocated accuracy loss budget, determined by estimates of the reduction in number of multiply-accumulate operations (in convolutional layers) and weights (in fully connected layers). Further, the structured LASSO variants in both convolutional and fully connected layers are explored within the smoothed LASSO framework and the tradeoffs involved are discussed. The efficacy of proposed algorithm in enhancing the sparsity within the allowed degradation in DNN accuracy and results obtained on structured LASSO variants are shown on MNIST, SVHN, CIFAR-10, and Imagenette datasets and on larger networks such as ResNet-50 and Mobilenet.

This paper presents a new time-domain technique for computing the noise-spectral density. The power-spectral density (PSD) is interpreted as the asymptotic value of the expected energy-spectral density per unit time. The methodology of stochastic differential equations is used to derive a set of ordinary differential equations for the expected energy-spectral density. This set of equations can then be integrated in time until the steady-state value of the PSD is obtained. The method can be used to find the noise spectrum in any circuit in which noise can be treated as a perturbation. The general nature of this algorithm has been illustrated in this paper by using it to get the noise-spectral density in switched-capacitor circuits, externally linear circuits and oscillators. The results match well with published experimental/analytical data. © 2004 IEEE.

Switched-capacitor circuits are periodically time-varying circuits and the noise at the output of these circuits is cyclostationary. This noise is therefore characterized by the average and harmonic spectral densities. In this paper, we extend the method proposed in a previous paper to compute the average and harmonic noise-spectral densities in periodically varying ciruits. We derive expressions for the average and harmonic spectral densities and use the mixed-frequency-time technique for the computation. The results for the average spectral density are compared with published results. The contribution of the harmonic spectral densities to the average noise-spectral density at the output of a cascaded block is estimated. © 2004 IEEE.