Anjan Chakravorty

In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is presented. The proposed modeling technique takes as inputs the dimensions of emitter fingers, shallow and deep trench isolations, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are validated against 3D TCAD simulations of multifinger bipolar transistors with and without trench isolations. Geometry scalability of the model is also demonstrated.

In this brief, we propose a step-by-step strategy to accurately estimate the finger temperature in a silicon-based multifinger bipolar transistor structure from conventional measurements. First we extract the nearly zero-power self-heating resistances (Rth,ii (Ta)) and thermal coupling factors (cij (Ta)) at a given ambient temperature. Now, by applying the superposition principle on these variables at nearly zero-power, where the linearity of the heat diffusion equation is preserved, we estimate an effective thermal resistance (Rth,i (Ta)) and the corresponding revised finger temperature Ti (Ta). Finally, the Kirchhoff's transformation on Ti (Ta) yields the true temperature at each finger (Ti (Ta,Pd)). The proposed extraction technique automatically includes the effects of back-end-of-line metal layers and different types of trenches present within the transistor structure. The technique is first validated against 3-D TCAD simulation results of bipolar transistors with different emitter dimensions and then applied on actual measured data obtained from the state-of-the-art multifinger SiGe HBT from STMicroelectronics B5T technology. It is observed that the superposition of raw measured data at around 40 mW power underestimates the true finger temperature by around 10%.

In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.

In this paper, we extend the model developed in part-I of this work to include the effects of the back-end-of-line (BEOL) metal layers and test its validity against on-wafer measurement results of SiGe heterojunction bipolar transistors (HBTs). First we modify the position dependent substrate temperature model of part-I by introducing a parameter to account for the upward heat flow through BEOL. Accordingly the coupling coefficient models for bipolar transistors with and without trench isolations are updated. The resulting modeling approach takes as inputs the dimensions of emitter fingers, shallow and deep trench isolation, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are first validated against 3D TCAD simulations including the effect of BEOL followed by validation against measured data obtained from state-of-art multifinger SiGe HBTs of different emitter geometries.

A prior estimate of the impact of thermal resistance from the back-end-of-line (BEOL) metallization layers is crucial for an accurate circuit design and thermally aware device design. This article presents a robust technique to extract the thermal resistance component originating from the BEOL metal layers in silicon germanium heterojunction bipolar transistors (SiGe HBTs). The proposed technique is first tested on data generated using analytical equations and later validated with 3-D TCAD simulation. The results clearly show that the exact contribution of the BEOL to the overall thermal resistance is captured in the proposed approach. Finally, we verified the method using measured data obtained from fabricated SiGe HBT structures using Infineon B11HFC technology. The extracted parameters show reasonable accuracy and consistency across different emitter dimensions and BEOL configurations.

Thermal behavior in multi-layered semiconductor structures like the one present in a Gallium Nitride high electron mobility transistor (GaN-HEMT) is investigated for the heat-flow towards the substrate. A compact analytical model is formulated to predict the peak as well as depth dependent temperature in the structure. Modeling results are verified against detailed three-dimensional TCAD thermal simulations of GaN-on-Si structures with GaN layer thickness of 3μm and Si substrate thickness of 100μm. Excellent modeling accuracy is observed for different heat source geometries and power dissipation. In addition, the proposed model is extended to estimate the static thermal coupling factor in multifinger transistors with high level of accuracy.

An efficient technique to extract the front-end-of-line and back-end-of-line components of the thermal resistance in bipolar transistors is proposed. The proposed approach is tested with the numerical simulations of silicon germanium HBTs corresponding to the STMicroelectronics B9MW process. We also predict the overestimate in the conventional thermal resistance models which neglects the thermal resistance contribution from the back-end-of-line. The results of the proposed extraction technique are observed to be in agreement with the numerical simulations for different emitter geometries.

In this work a simple, analytic model is proposed to estimate the depth-dependent temperature profile in multilayered power electronic systems. The proposed model considers both upward and downward heat flow, with heat conduction within the structure and heat convection at the heat sink boundaries. The proposed model is verified with simulations and experimental data obtained on multi-layered power devices like solar cell and a power converter having an insulated gated bipolar transistor (IGBT) and a diode. Besides being computationally efficient, the proposed analytical model predicts the temperature profile as accurate as obtained from commercial numerical simulators. The experimental verification of the model for a multi-layered solar cell structure is also presented.

In this paper, we propose an efficient model for dynamic self-heating and thermal coupling in a multifinger transistor system. Essentially, the proposed model is an improvement over a state-of-the-art existing model from the viewpoint of simulation time. Verilog-A implementation of the proposed model does not require to use any voltage controlled voltage source. In a multifinger transistor system, with $n$ emitter fingers, our model uses $3n$ extra nodes in Verilog-A implementation whereas it is $2n^{2}-n$ for the state-of-the-art model. Note that our model requires no extra nodes for implementing the thermal coupling effects. We present that the transient simulation results of our model are identical with those of the state-of-the-art model. Electrothermal simulation using the proposed thermal model shows good agreement with the measured data. It is found that the proposed model simulates more than 40% faster compared with the existing model for a ring oscillator circuit.

In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon-germanium HBTs fabricated in the STMicroelectronics B9MW technology.