Anjan Chakravorty

This paper investigates alternative topologies of silicon germanium heterojunction bipolar transistors designed and fabricated in the state-of-the-art BiCMOS process from STMicroelectronics for improved safe-operating characteristics. Electrical and thermal behaviors of various structures are analyzed and compared, along with a detailed discussion on drawbacks and advantages. The test structures under study are different in terms of emitter-finger layouts as well as the metal stacks in the back-end-of-line. It is observed that the multifinger transistor structures having nonuniform finger lengths with wider area enclosed by the deep trench and higher metallization stacks yield an improved thermal behavior. Therefore, the safe-operating area of multifinger transistors can be extended without degrading the RF performances.

In this brief, we propose a step-by-step strategy to accurately estimate the finger temperature in a silicon-based multifinger bipolar transistor structure from conventional measurements. First we extract the nearly zero-power self-heating resistances (Rth,ii (Ta)) and thermal coupling factors (cij (Ta)) at a given ambient temperature. Now, by applying the superposition principle on these variables at nearly zero-power, where the linearity of the heat diffusion equation is preserved, we estimate an effective thermal resistance (Rth,i (Ta)) and the corresponding revised finger temperature Ti (Ta). Finally, the Kirchhoff's transformation on Ti (Ta) yields the true temperature at each finger (Ti (Ta,Pd)). The proposed extraction technique automatically includes the effects of back-end-of-line metal layers and different types of trenches present within the transistor structure. The technique is first validated against 3-D TCAD simulation results of bipolar transistors with different emitter dimensions and then applied on actual measured data obtained from the state-of-the-art multifinger SiGe HBT from STMicroelectronics B5T technology. It is observed that the superposition of raw measured data at around 40 mW power underestimates the true finger temperature by around 10%.

In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.

A prior estimate of the impact of thermal resistance from the back-end-of-line (BEOL) metallization layers is crucial for an accurate circuit design and thermally aware device design. This article presents a robust technique to extract the thermal resistance component originating from the BEOL metal layers in silicon germanium heterojunction bipolar transistors (SiGe HBTs). The proposed technique is first tested on data generated using analytical equations and later validated with 3-D TCAD simulation. The results clearly show that the exact contribution of the BEOL to the overall thermal resistance is captured in the proposed approach. Finally, we verified the method using measured data obtained from fabricated SiGe HBT structures using Infineon B11HFC technology. The extracted parameters show reasonable accuracy and consistency across different emitter dimensions and BEOL configurations.

In this paper, we propose an efficient model for dynamic self-heating and thermal coupling in a multifinger transistor system. Essentially, the proposed model is an improvement over a state-of-the-art existing model from the viewpoint of simulation time. Verilog-A implementation of the proposed model does not require to use any voltage controlled voltage source. In a multifinger transistor system, with $n$ emitter fingers, our model uses $3n$ extra nodes in Verilog-A implementation whereas it is $2n^{2}-n$ for the state-of-the-art model. Note that our model requires no extra nodes for implementing the thermal coupling effects. We present that the transient simulation results of our model are identical with those of the state-of-the-art model. Electrothermal simulation using the proposed thermal model shows good agreement with the measured data. It is found that the proposed model simulates more than 40% faster compared with the existing model for a ring oscillator circuit.

In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon-germanium HBTs fabricated in the STMicroelectronics B9MW technology.

Effects of the back-end-of-line layers up to metal-1 on the self-heating and thermal coupling in a multi-finger silicon germanium heterojunction bipolar transistor (SiGe MFT) are investigated. It is observed that the rise in junction temperature is overestimated if the BEOL effects are not considered. A new method for estimating the thermal coupling coefficients is proposed emulating the real operating condition. The proposed methodology demonstrates that the thermal coupling is increased in real operating condition and the estimated coupling coefficients are almost independent of the dissipated power. Further an empirical closed-form formulation is proposed for estimating the coupling coefficients analytically and for subsequently using in compact model simulation. The formulation is found to predict the coefficients quite accurately. Compact model simulations using the analytically obtained coupling coefficients show excellent model agreement with the static and dynamic 3D TCAD simulation data for junction temperature. Finally the model is validated against the measured data corresponding to an SiGe MFT fabricated using B55 technology from ST microelectronics.

An accurate analytic model is proposed for estimating the junction temperature and thermal resistance in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) including the back-end-of-line (BEOL) metal layers. The model uses an average value of thermal conductivity in order to include the temperature dependence of thermal resistance. The parameters corresponding to the thermal conductivity and the BEOL thermal resistance used in the model are extracted following a recently reported methodology. The proposed model is scalable in nature and verification with experimental data shows an excellent accuracy across different emitter geometries of SiGe HBTs fabricated in STMicroelectronics B9MW technology. Compact model simulations show that the proposed model simulates around 23% faster compared with an existing state-of-the-art iterative method.