Now showing 1 - 10 of 16
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    Innovative SiGe HBT Topologies with Improved Electrothermal Behavior
    (01-07-2016)
    D'Esposito, Rosario
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    Frégonèse, Sébastien
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    Chevalier, Pascal
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    Céli, Didier
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    Zimmer, Thomas
    This paper investigates alternative topologies of silicon germanium heterojunction bipolar transistors designed and fabricated in the state-of-the-art BiCMOS process from STMicroelectronics for improved safe-operating characteristics. Electrical and thermal behaviors of various structures are analyzed and compared, along with a detailed discussion on drawbacks and advantages. The test structures under study are different in terms of emitter-finger layouts as well as the metal stacks in the back-end-of-line. It is observed that the multifinger transistor structures having nonuniform finger lengths with wider area enclosed by the deep trench and higher metallization stacks yield an improved thermal behavior. Therefore, the safe-operating area of multifinger transistors can be extended without degrading the RF performances.
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    Low-Frequency Noise in Advanced SiGe:C HBTs-Part I: Analysis
    (01-09-2016)
    Mukherjee, Chhandak
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    Jacquet, Thomas
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    Zimmer, Thomas
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    Bock, Josef
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    Aufinger, Klaus
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    Maneux, Cristell
    In this paper, we present extensive characterization of low-frequency noise in advanced silicon germanium heterojunction bipolar transistors. We demonstrate the extraction methodology of base and collector noise spectral densities for a wide range of transistor geometries. In addition to 1/f noise, generation-recombination (G-R) mechanisms are observed at low bias in the base current noise. Their existence is confirmed by Random Telegraph Signal (RTS) noise measurements. 1/f and G-R components are extracted from the base current noise spectra and their bias dependencies are studied. Finally, base current noise spectral densities measured at the same base current density in different geometries are compared to study the individual contribution of 1/f noise from the periphery as well as the intrinsic device. Part II of this paper will discuss the modeling aspects and noise correlation.
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    Publication
    TCAD simulation and assessment of anomalous deflection in measured S-parameters of SiGe HBTs in THz range
    (01-11-2019)
    Panda, Soumya Ranjan
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    Fregonese, Sebastien
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    Zimmer, Thomas
    In this paper, we have assessed the RF measurements of SiGe HBTs upto 500 GHz using TCAD simulation for the first time. In order to bring confidence in simulation, the device geometries and doping profiles are captured in the simulation deck. Then all the basic DC and RF properties are calibrated with the measured data for two different geometries. Additionally the simulated unilateral gain and small signal current gain are also brought in agreement with the corresponding measured data at different bias voltages for both the devices. Finally bias and frequency dependent S- parameter measurements are compared with the TCAD simulation and resulting issues are discussed.
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    Publication
    Collector-substrate modeling of SiGe HBTs up to THz range
    (01-11-2019)
    Saha, Bishwadeep
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    Fregonese, Sebastien
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    Panda, Soumya Ranjan
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    Celi, Didier
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    Zimmer, Thomas
    The undesired behavior of the substrate significantly affects the output impedance of the device; hence degrades circuit performance mainly in the high frequency regime. Therefore, for high-speed and RF circuits, collector-substrate modeling has to be sufficiently accurate. In this paper, an improved collector-substrate equivalent circuit model is proposed. The circuit model elements are physics based and are calculated from technological data. The validity of the equivalent circuit has been verified by on-wafer measurements of an SiGe HBT fabricated in B55 technology up to 330 GHz, the highest frequency reported so far for collector-substrate modeling. The proposed substrate network can be considered as an extension of the latest large-signal HICUM model (L2v2.4).
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    Modeling non-quasi-static effects in siGe HBTs using improved charge partitioning scheme
    (09-07-2012)
    Augustine, Noel
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    Kumar, Khamesh
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    Bhattacharyya, Arkaprava
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    Zimmer, Thomas
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    The applicability of a partitioned-charge-based non-quasi-static (NQS) model is investigated using exact solutions for 1-D bipolar transistors. Limitations of the model to accurately predict y21(ω) are overcome by further delaying the partitioned minority charge associated with the collector. A corresponding small-signal time-domain model is derived. The proposed model effectively includes the delays within both the quasi-neutral base and base-collector space-charge regions. Using only two extra nodes over the quasi-static bipolar transistor model HICUM, the NQS model is implemented using Verilog-A. The simplicity of the model yields straightforward parameter extraction techniques. Modeling results show excellent agreement with numerically simulated data. © 2012 IEEE.
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    Analytic Estimation of Thermal Resistance in HBTs
    (01-01-2016) ;
    D'Esposito, Rosario
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    Balanethiram, Suresh
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    Frégonèse, Sébastien
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    Zimmer, Thomas
    In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.
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    Extracting the FEOL and BEOL components of thermal resistance in SiGe HBTs
    (18-10-2017)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Zimmer, Thomas
    An efficient technique to extract the front-end-of-line and back-end-of-line components of the thermal resistance in bipolar transistors is proposed. The proposed approach is tested with the numerical simulations of silicon germanium HBTs corresponding to the STMicroelectronics B9MW process. We also predict the overestimate in the conventional thermal resistance models which neglects the thermal resistance contribution from the back-end-of-line. The results of the proposed extraction technique are observed to be in agreement with the numerical simulations for different emitter geometries.
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    Efficient modeling of distributed dynamic self-heating and thermal coupling in multifinger SiGe HBTs
    (01-09-2016)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Céli, Didier
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    Zimmer, Thomas
    In this paper, we propose an efficient model for dynamic self-heating and thermal coupling in a multifinger transistor system. Essentially, the proposed model is an improvement over a state-of-the-art existing model from the viewpoint of simulation time. Verilog-A implementation of the proposed model does not require to use any voltage controlled voltage source. In a multifinger transistor system, with $n$ emitter fingers, our model uses $3n$ extra nodes in Verilog-A implementation whereas it is $2n^{2}-n$ for the state-of-the-art model. Note that our model requires no extra nodes for implementing the thermal coupling effects. We present that the transient simulation results of our model are identical with those of the state-of-the-art model. Electrothermal simulation using the proposed thermal model shows good agreement with the measured data. It is found that the proposed model simulates more than 40% faster compared with the existing model for a ring oscillator circuit.
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    Extraction of BEOL Contributions for Thermal Resistance in SiGe HBTs
    (01-03-2017)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Zimmer, Thomas
    In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon-germanium HBTs fabricated in the STMicroelectronics B9MW technology.
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    Publication
    Efficient models for non-quasi-static effects and correlated noise in SiGe HBTs
    (01-12-2012)
    Augustine, Noel
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    Kumar, Khamesh
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    Bhattacharyya, Arkaprava
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    Zimmer, Thomas
    The capability of a single CR sub-circuit to model a wide range of non-quasi-static (NQS) delays in silicon germanium heterojunction bipolar transistors is explored. A comparative study is carried out to show that the suitable use of a single CR sub-circuit following the partitioned-charge-based approach can replace the popularly used CR-LCR combination to model both the input and output NQS effects. Based on this NQS model, a correlated noise model is developed, which requires only three additional nodes for implementation in Verilog-A. Results show excellent agreement with numerically simulated data. © 2012 IEEE.