Now showing 1 - 4 of 4
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    Publication
    Extracting the FEOL and BEOL components of thermal resistance in SiGe HBTs
    (18-10-2017)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Zimmer, Thomas
    An efficient technique to extract the front-end-of-line and back-end-of-line components of the thermal resistance in bipolar transistors is proposed. The proposed approach is tested with the numerical simulations of silicon germanium HBTs corresponding to the STMicroelectronics B9MW process. We also predict the overestimate in the conventional thermal resistance models which neglects the thermal resistance contribution from the back-end-of-line. The results of the proposed extraction technique are observed to be in agreement with the numerical simulations for different emitter geometries.
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    Publication
    Efficient modeling of static self-heating and thermal-coupling in multi-finger SiGe HBTs
    (30-11-2015)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Zimmer, Thomas
    A computationally efficient model for static self-heating and thermal coupling in a multi-finger bipolar transistor is proposed. Compared to an existing state-of-the-art model, our model differs only in the implementation strategy keeping the physical basis intact. The formulated model is implemented in Verilog-A without using any voltage controlled voltage sources. Temperature dependence of the thermal resistances are considered within the framework of the model. The number of extra nodes in our model reduces to 2n from n2 required in the state-of-the-art model with n as the number of emitter fingers in a transistor. The simulation results of our model are found to be identical with those of the state-of-the-art model demonstrating the capability of accurately considering the static self-heating and thermal coupling in a simple way. The model is found to accurately predict the measured data of a five-finger transistor. It is found that in high current operating regimes, our five finger transistor model simulates around 11% faster compared with the state-of-the-art model.
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    Publication
    An improved scalable self-consistent iterative model for thermal resistance in SiGe HBTs
    (08-11-2016)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Zimmer, Thomas
    In this paper we present an improved self-consistent iterative model for thermal resistance in SiGe HBTs. The proposed model evaluates both the upward and downward heat dissipation from the heat source located at the base-collector junction. Along with the temperature dependency, thermal conductivity degradation due to heavy doping and Ge composition in the base region is included in the proposed model. It is observed that the model accuracy is improved once these physical effects are included along with the upward heat diffusion. Scalability of the proposed model is validated with the measured data for different emitter geometries.
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    Publication
    Reliable Technology Evaluation of SiGe HBTs and MOSFETs: FMAXEstimation from Measured Data
    (01-01-2021)
    Saha, Bishwadeep
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    Fregonese, Sebastien
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    Heinemann, Bernd
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    Scheer, Patrick
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    Chevalier, Pascal
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    Aufinger, Klaus
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    Zimmer, Thomas
    Maximum oscillation frequency ( fMAX ) of mm-wave transistors is one of the key figures of merit (FOMs) for evaluating the HF-performance of a given technology. However, accurate measurements of fMAX are very difficult. Determination of fMAX is significantly affected by the measurement uncertainties in the admittance ( y ) parameters. In order to get rid of the random measurement error and to obtain a reliable and stable fMAX value, the frequency dependent y -parameters are described by rational functions formulated from the small-signal hybrid π -model of the transistor under investigation. The parameters of these functions are determined following a least square error technique that minimizes the functional error with the measured data. The approach is especially useful for a fast and reliable evaluation of fMAX value. Devices from two different SiGe and an FDSOI (Fully Depleted Silicon On Insulator) MOS technology are measured and stable fMAX values are estimated following this approach.