Anjan Chakravorty

An existing water distribution network (WDN) may need to be expanded by adding a sub-network for the newly developed areas. The size of the problem becomes larger when the stochastic nature of domestic demands, optimal design and layouts, control, and operation of various hydraulic components are considered. In this study, the single-port Thevenin theorem used in electrical circuits is applied to reduce a large WDN with its equivalent network consisting of a single source and a single pipe. The equivalent network is then attached to a sub-network for focused analysis. The accuracy and robustness of the proposed network reduction procedure are investigated on realistic WDNs for various sub-network demands using steady and extended period simulations. A simplified approach is also presented to achieve the same objective but constrained by the level of accuracy. Hydraulic engineers can use the proposed methodology as an efficient network reduction tool.

In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is presented. The proposed modeling technique takes as inputs the dimensions of emitter fingers, shallow and deep trench isolations, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are validated against 3D TCAD simulations of multifinger bipolar transistors with and without trench isolations. Geometry scalability of the model is also demonstrated.

In this article, the effect of charge partitioning in a silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor on its nonlinearity model is investigated. It is found that the prediction of the third-order intermodulation distortion (IM3) depends on the model equivalent circuit (EC) and appropriate charge assignments at various nodes therein. The investigation is carried out using a highly accurate static model of LDMOS along with a couple of different charge-partitioning schemes in order to single out their effects on the nonlinearity model behavior. We observe that charge partitioning in a more flexible EC framework yields an improved IM3 prediction when compared with the TCAD simulated results.

In this paper, we present extensive random telegraph signal (RTS) noise characterization in SiGe heterojunction bipolar transistors. RTS noise, observed at the base, originates at the emitter periphery while at the collector side distinct RTS noise is observed at high-injection that originates from the traps in the shallow trench regions. Time constants extracted from RTS during aging tests allow understanding of trap dynamics and new defect formation within the device structure. This paper provides the first demonstration of RTS measurements during accelerated aging tests to study and understand generation of defects under bias stress in SiGe HBTs operating at the limit of their safe-operating area.

This paper investigates alternative topologies of silicon germanium heterojunction bipolar transistors designed and fabricated in the state-of-the-art BiCMOS process from STMicroelectronics for improved safe-operating characteristics. Electrical and thermal behaviors of various structures are analyzed and compared, along with a detailed discussion on drawbacks and advantages. The test structures under study are different in terms of emitter-finger layouts as well as the metal stacks in the back-end-of-line. It is observed that the multifinger transistor structures having nonuniform finger lengths with wider area enclosed by the deep trench and higher metallization stacks yield an improved thermal behavior. Therefore, the safe-operating area of multifinger transistors can be extended without degrading the RF performances.

In this paper, we develop a correlated noise model for bipolar transistors from an accurate nonquasi-static model. The proposed noise model includes the signal delay through base-collector space-charge region and is implemented using four extra nodes. We also present a simplified version of the same model that requires only two extra nodes. A further simplified version that uses only one extra node is found to be identical with a state-of-the-art correlated noise model. When compared with the device simulation data, our proposed models show improved accuracy compared with the existing state-of-the-art noise models.

In this paper, we present extensive characterization of low-frequency noise in advanced silicon germanium heterojunction bipolar transistors. We demonstrate the extraction methodology of base and collector noise spectral densities for a wide range of transistor geometries. In addition to 1/f noise, generation-recombination (G-R) mechanisms are observed at low bias in the base current noise. Their existence is confirmed by Random Telegraph Signal (RTS) noise measurements. 1/f and G-R components are extracted from the base current noise spectra and their bias dependencies are studied. Finally, base current noise spectral densities measured at the same base current density in different geometries are compared to study the individual contribution of 1/f noise from the periphery as well as the intrinsic device. Part II of this paper will discuss the modeling aspects and noise correlation.

In this brief, we propose a step-by-step strategy to accurately estimate the finger temperature in a silicon-based multifinger bipolar transistor structure from conventional measurements. First we extract the nearly zero-power self-heating resistances (Rth,ii (Ta)) and thermal coupling factors (cij (Ta)) at a given ambient temperature. Now, by applying the superposition principle on these variables at nearly zero-power, where the linearity of the heat diffusion equation is preserved, we estimate an effective thermal resistance (Rth,i (Ta)) and the corresponding revised finger temperature Ti (Ta). Finally, the Kirchhoff's transformation on Ti (Ta) yields the true temperature at each finger (Ti (Ta,Pd)). The proposed extraction technique automatically includes the effects of back-end-of-line metal layers and different types of trenches present within the transistor structure. The technique is first validated against 3-D TCAD simulation results of bipolar transistors with different emitter dimensions and then applied on actual measured data obtained from the state-of-the-art multifinger SiGe HBT from STMicroelectronics B5T technology. It is observed that the superposition of raw measured data at around 40 mW power underestimates the true finger temperature by around 10%.

In this paper, we present the operation principle of an organic metal-insulator-semiconductor (MIS) capacitor where the organic semiconductor is undoped. In spite of a low charge concentration within the semiconductor, this device exhibits a capacitance variation with respect to the applied gate voltage yielding the capacitance-voltage characteristics similar to that of a traditional MIS capacitor based on the doped semiconductor. A physics-based model is developed to derive the charge concentration, surface potential, and the capacitance of the organic MIS capacitor. The model is validated with TCAD simulation results as well as with experimental data obtained from the fabricated organic MIS capacitor consisting of poly(4-vinylphenol) and poly(3-hexylthiophene-2, 5-diyl) as an insulator and a semiconductor, respectively.

In this paper, we report an accurate quasi-saturation model and a nodal charge model for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (SOI-LDMOS) transistors. First, a model of a 2-D SOI resistor under velocity saturation is developed, which is subsequently incorporated into the drift region of an LDMOS transistor to predict the quasi-saturation effect. The gate-voltage dependence of the quasi-saturation current is also modeled. Second, we propose a new nodal charge model to describe the dynamic behavior of the device. Comparisons of modeling results with device simulation data show that the proposed model is accurate over a wide range of bias. Scalability of the model with respect to the length of the drift region under the field oxide is also demonstrated. Finally, the model is validated under device self-heating conditions and by comparing it with the experimental data.