Anjan Chakravorty

In this brief, we propose a step-by-step strategy to accurately estimate the finger temperature in a silicon-based multifinger bipolar transistor structure from conventional measurements. First we extract the nearly zero-power self-heating resistances (Rth,ii (Ta)) and thermal coupling factors (cij (Ta)) at a given ambient temperature. Now, by applying the superposition principle on these variables at nearly zero-power, where the linearity of the heat diffusion equation is preserved, we estimate an effective thermal resistance (Rth,i (Ta)) and the corresponding revised finger temperature Ti (Ta). Finally, the Kirchhoff's transformation on Ti (Ta) yields the true temperature at each finger (Ti (Ta,Pd)). The proposed extraction technique automatically includes the effects of back-end-of-line metal layers and different types of trenches present within the transistor structure. The technique is first validated against 3-D TCAD simulation results of bipolar transistors with different emitter dimensions and then applied on actual measured data obtained from the state-of-the-art multifinger SiGe HBT from STMicroelectronics B5T technology. It is observed that the superposition of raw measured data at around 40 mW power underestimates the true finger temperature by around 10%.

Limitations of existing models for collector current noise power spectral density of silicon germanium heterojunction bipolar transistors are figured out and suitable model modifications are proposed based on non-quasi-static delay and self-heating effects. Modeling results show excellent agreement with device simulated data obtained using hydrodynamic technique. © 2012 IEEE.

In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.

A prior estimate of the impact of thermal resistance from the back-end-of-line (BEOL) metallization layers is crucial for an accurate circuit design and thermally aware device design. This article presents a robust technique to extract the thermal resistance component originating from the BEOL metal layers in silicon germanium heterojunction bipolar transistors (SiGe HBTs). The proposed technique is first tested on data generated using analytical equations and later validated with 3-D TCAD simulation. The results clearly show that the exact contribution of the BEOL to the overall thermal resistance is captured in the proposed approach. Finally, we verified the method using measured data obtained from fabricated SiGe HBT structures using Infineon B11HFC technology. The extracted parameters show reasonable accuracy and consistency across different emitter dimensions and BEOL configurations.

An accurate closed-form analytical model is proposed to predict the junction temperature and thermal resistance of silicon germanium heterojunction bipolar transistors, including the effect of back-end-of-line (BEOL) metal layers. A linear approximation is used in a thermal resistivity model of silicon to reduce the model complexity. A simple method is proposed to extract the necessary model parameters along with the BEOL thermal resistance. The model is validated with the TCAD simulation, and the scalability of the model is verified by the comparison with experimental data for different device geometries. The model shows excellent agreement with both TCAD simulation (without BEOL) and experimental data (with BEOL).

An efficient technique to extract the front-end-of-line and back-end-of-line components of the thermal resistance in bipolar transistors is proposed. The proposed approach is tested with the numerical simulations of silicon germanium HBTs corresponding to the STMicroelectronics B9MW process. We also predict the overestimate in the conventional thermal resistance models which neglects the thermal resistance contribution from the back-end-of-line. The results of the proposed extraction technique are observed to be in agreement with the numerical simulations for different emitter geometries.

In this paper, we propose an efficient model for dynamic self-heating and thermal coupling in a multifinger transistor system. Essentially, the proposed model is an improvement over a state-of-the-art existing model from the viewpoint of simulation time. Verilog-A implementation of the proposed model does not require to use any voltage controlled voltage source. In a multifinger transistor system, with $n$ emitter fingers, our model uses $3n$ extra nodes in Verilog-A implementation whereas it is $2n^{2}-n$ for the state-of-the-art model. Note that our model requires no extra nodes for implementing the thermal coupling effects. We present that the transient simulation results of our model are identical with those of the state-of-the-art model. Electrothermal simulation using the proposed thermal model shows good agreement with the measured data. It is found that the proposed model simulates more than 40% faster compared with the existing model for a ring oscillator circuit.

In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon-germanium HBTs fabricated in the STMicroelectronics B9MW technology.

We present a compact modeling framework to optimize finger spacing for improving the thermal stability in multifinger bipolar transistors with shallow-trench isolation. First, we present an accurate physics-based model for total junction temperature in all the fingers of a transistor. Other than validating the model with 3-D TCAD simulations and measured data, we demonstrate its efficacy to achieve finger spacing optimization with the aid of an iterative algorithm. Since the proposed technique is scalable from the viewpoint of the number of fingers within a transistor and their geometries, the proposed framework is found to work seamlessly for various emitter finger numbers.

In this paper we present an improved self-consistent iterative model for thermal resistance in SiGe HBTs. The proposed model evaluates both the upward and downward heat dissipation from the heat source located at the base-collector junction. Along with the temperature dependency, thermal conductivity degradation due to heavy doping and Ge composition in the base region is included in the proposed model. It is observed that the model accuracy is improved once these physical effects are included along with the upward heat diffusion. Scalability of the proposed model is validated with the measured data for different emitter geometries.