Now showing 1 - 10 of 10
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    Modeling collector current noise PSD of SiGe HBTs including self-heating and non-quasi-static effects
    (12-12-2012)
    Kumar, Khamesh
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    Limitations of existing models for collector current noise power spectral density of silicon germanium heterojunction bipolar transistors are figured out and suitable model modifications are proposed based on non-quasi-static delay and self-heating effects. Modeling results show excellent agreement with device simulated data obtained using hydrodynamic technique. © 2012 IEEE.
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    Analytic Estimation of Thermal Resistance in HBTs
    (01-01-2016) ;
    D'Esposito, Rosario
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    Balanethiram, Suresh
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    Frégonèse, Sébastien
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    Zimmer, Thomas
    In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.
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    A Pragmatic Approach to Modeling Self-Heating Effects in SiGe HBTs
    (01-12-2017)
    Yadav, Shon
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    An accurate closed-form analytical model is proposed to predict the junction temperature and thermal resistance of silicon germanium heterojunction bipolar transistors, including the effect of back-end-of-line (BEOL) metal layers. A linear approximation is used in a thermal resistivity model of silicon to reduce the model complexity. A simple method is proposed to extract the necessary model parameters along with the BEOL thermal resistance. The model is validated with the TCAD simulation, and the scalability of the model is verified by the comparison with experimental data for different device geometries. The model shows excellent agreement with both TCAD simulation (without BEOL) and experimental data (with BEOL).
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    Extracting the FEOL and BEOL components of thermal resistance in SiGe HBTs
    (18-10-2017)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Zimmer, Thomas
    An efficient technique to extract the front-end-of-line and back-end-of-line components of the thermal resistance in bipolar transistors is proposed. The proposed approach is tested with the numerical simulations of silicon germanium HBTs corresponding to the STMicroelectronics B9MW process. We also predict the overestimate in the conventional thermal resistance models which neglects the thermal resistance contribution from the back-end-of-line. The results of the proposed extraction technique are observed to be in agreement with the numerical simulations for different emitter geometries.
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    Publication
    Efficient modeling of distributed dynamic self-heating and thermal coupling in multifinger SiGe HBTs
    (01-09-2016)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Céli, Didier
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    Zimmer, Thomas
    In this paper, we propose an efficient model for dynamic self-heating and thermal coupling in a multifinger transistor system. Essentially, the proposed model is an improvement over a state-of-the-art existing model from the viewpoint of simulation time. Verilog-A implementation of the proposed model does not require to use any voltage controlled voltage source. In a multifinger transistor system, with $n$ emitter fingers, our model uses $3n$ extra nodes in Verilog-A implementation whereas it is $2n^{2}-n$ for the state-of-the-art model. Note that our model requires no extra nodes for implementing the thermal coupling effects. We present that the transient simulation results of our model are identical with those of the state-of-the-art model. Electrothermal simulation using the proposed thermal model shows good agreement with the measured data. It is found that the proposed model simulates more than 40% faster compared with the existing model for a ring oscillator circuit.
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    Extraction of BEOL Contributions for Thermal Resistance in SiGe HBTs
    (01-03-2017)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Zimmer, Thomas
    In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon-germanium HBTs fabricated in the STMicroelectronics B9MW technology.
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    An improved scalable self-consistent iterative model for thermal resistance in SiGe HBTs
    (08-11-2016)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Zimmer, Thomas
    In this paper we present an improved self-consistent iterative model for thermal resistance in SiGe HBTs. The proposed model evaluates both the upward and downward heat dissipation from the heat source located at the base-collector junction. Along with the temperature dependency, thermal conductivity degradation due to heavy doping and Ge composition in the base region is included in the proposed model. It is observed that the model accuracy is improved once these physical effects are included along with the upward heat diffusion. Scalability of the proposed model is validated with the measured data for different emitter geometries.
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    Publication
    Accurate Modeling of Thermal Resistance for On-Wafer SiGe HBTs Using Average Thermal Conductivity
    (01-09-2017)
    Balanethiram, Suresh
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    D'Esposito, Rosario
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    Fregonese, Sebastien
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    Celi, Didier
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    Zimmer, Thomas
    An accurate analytic model is proposed for estimating the junction temperature and thermal resistance in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) including the back-end-of-line (BEOL) metal layers. The model uses an average value of thermal conductivity in order to include the temperature dependence of thermal resistance. The parameters corresponding to the thermal conductivity and the BEOL thermal resistance used in the model are extracted following a recently reported methodology. The proposed model is scalable in nature and verification with experimental data shows an excellent accuracy across different emitter geometries of SiGe HBTs fabricated in STMicroelectronics B9MW technology. Compact model simulations show that the proposed model simulates around 23% faster compared with an existing state-of-the-art iterative method.
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    Publication
    Analysis of electro-thermal instability in bipolar transistors
    (30-09-2015)
    Balanethiram, Suresh
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    This paper illustrates an analytical method to determine the electro-thermal instability due to self-heating and impact ionization in terms of dissipated power and junction temperature. The analysis is carried out for single transistors (corresponding to silicon and gallium arsenide technologies) as well as for scaled devices to appreciate the use of dissipated power for determining the safe operating region of bipolar transistors. Our analysis is supported by the already reported numerical, PSPICE and experimental data from the literature and shows that at usual operating conditions the small geometry devices have less safe operating region compared to the larger ones.
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    Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors
    (01-10-2016)
    Nikhil, Krishnan Nadar Savithry
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    In this paper, for the first time, we report a nonmonotonic dependence of the snapback voltage (Vsb) on the buried oxide thickness (tBOX) in silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors. Step-by-step analysis of this effect is carried out by decoupling the self-heating and impact-ionization effects that cause the turning ON of the parasitic bipolar junction transistor (BJT) and subsequently the snapback effect. It is observed that for LDMOS transistors with low tBOX, Vsb increases with increase in tBOX due to reduction in drain current density as well as reduced impact ionization at higher lattice temperature. On the other hand, for high tBOX, Vsb reduces with the increase in tBOX due to early switching ON of the parasitic BJT at higher temperature. Therefore, it is possible to find an optimum value of tBOX to obtain the highest Vsb for an SOI-LDMOS transistor. An interesting observation is that with proper choice of tBOX, the safe operating area in SOI-LDMOS can be more than that of the corresponding bulk-LDMOS. A physics-based compact model is developed and implemented in Verilog-A. When compared with the Technology Computer Aided Design simulated results, our model exhibits high level of accuracy.