Veezhinathan Kamakoti

In sub-70 nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. This paper proposes a Power-Managed Scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. Some practical implementation challenges that arise when the proposed scheme is employed on industrial designs are also discussed. Experimental results on benchmark circuits and industrial designs show that employing the proposed technique leads to a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies. Copyright © 2008 American Scientific Publishers All rights reserved.

System test and online test techniques are aggressively being used in today's SoCs for improved test quality and reliability (e.g., aging/soft-error robustness). With gaining popularity of vertical integration such as 2.5D and 3D, in the semiconductor industry, ensuring thermal safety of SoCs during these test modes poses a challenge. In this paper, we propose a dynamic test scheduling mechanism for system tests and/or online test that uses dynamic feedback from on-chip thermal sensors to control temperature during shift (or scan) and capture, thereby ensuring thermal-safe conditions while applying the test patterns. The proposed technique is a closed loop test application scheme that eliminates the need for separate thermal simulation of test patterns at design stage. The technique also enables granular field-level configuration of thermal limits, so that different units across multiple cores are subjected to customized thermal profiles. Results from implementation of the proposed schemes on a 4-layer, 16-core, 12.8 million gates, OpenSparc S1 processor subsystem are presented. Copyright © 2012 American Scientific Publishers. All rights reserved.

The advancement in the semiconductor manufacturing process has reduced the device dimensions, which in turn has reduced design and manufacturing costs of the Integrated Chips (IC). This has accelerated the IC penetration in automobiles, health care and safety critical systems. However, the smaller device dimensions have made the ICs vulnerable to soft-errors. The sequential cells in a given design contribute significantly to its soft-error rate (SER). Some of the soft-errors get masked and do not cause any adverse impact. The masking can occur due to logic or timing reasons. This paper presents a flow that uses the Timing Vulnerability Factor (TVF) and Architecture Vulnerability Factor (AVF) of the sequential instances in a given design to reduce its soft-error rate (SER). The paper proposes a novel method to efficiently compute the TVF and AVF parameters followed by a linear programming technique that uses these parameters to reduce the SER of the given design. Using the proposed technique, we have reduced the sequential cell contribution to the SER of an in-house IP design by 36% for an increase of 9% in sequential cells area.

Modern SoC devices use elaborate power management strategies in functional mode, because not all IP blocks can be functional at the same time. Cost considerations often do not permit overdesigning the power supply infrastructure for test mode or using expensive flip-chip packaging to avoid the problem. Test application must not overexercise the power supply grids, lest the tests damage the device or lead to false test failures. The problem of debugging a delay test failure can therefore be highly complex. The problem is aggravated by on-chip variations in technologies below 100 nm. However, it's possible to avoid false delay test failures by generating safe patterns that are tolerant to on-chip variations. The authors propose a framework for power-safe pattern generation that uses power grid information and regional constraints on switching activity. Experimental results with benchmark circuits demonstrate the effectiveness of this framework. © 2007 IEEE.

With increasing use of low cost wire-bond packages for mobile devices, excessive dynamic IR-drop may cause tests to fail on the tester. Identifying and debugging such scan test failures is a very complex and effort-intensive process. A better solution is to generate correct-by-construction "power-safe" patterns. Moreover, with glitch power contributing to a significant component of dynamic power, pattern generation needs to be timing-aware to minimize glitching. In this paper, we propose a timing-based, power and layout-aware pattern generation technique that minimizes both global and localized switching activity. Techniques are also proposed for power-profiling and optimizing an initial pattern set to obtain a power-safe pattern set, with the addition of minimal patterns. The proposed technique also comprehends irregular power grid topologies for constraints on localized switching activity. Experiments on ISCAS benchmark circuits reveal the effectiveness of the proposed scheme. © 2007 EDAA.

With increasing integration of capabilities into mobile application processors, a host of imaging operations that were earlier performed in software are now implemented in hardware. Though imaging applications are inherently error resilient, the complexity of such designs has increased over time and thus identifying logic that can be leveraged for energy-quality trade-offs has become difficult. The paper proposes a Progressive Configuration Aware (ProCA) criticality analysis framework, that is 10X faster than the state-of-the-art, to identify logic which is functionally-critical to output quality. This accounts for the various modes of operation of the design. Through such a framework, we demonstrate how a low powered tunable stochastic design can be derived. The proposed methodology uses layered synthesis and voltage scaling mechanisms as primary tools for power reduction. We demonstrate the proposed methodology on a production quality imaging IP implemented in 28nm low leakage technology. For the tunable stochastic imaging IP, we gain up to 10.57% power reduction in exact mode and up to 32.53% power reduction in error tolerant mode (30dB PSNR), with negligible design overhead. © 2014 IEEE.

With the possible end of the Moore's Law at the horizon, Approximate Computing has gathered momentum over the past years as a possible alternative for low power designs. Approximate computing trades better energy performance for tolerable inaccuracies at the output of the design. In this paper, we propose an application independent automated flow that converts a given design into an approximate version using either voltage scaling or power gating based techniques. The proposed model is shown to be effective for designing low power media type IPs (Intellectual Properties) based ASICs (Application Specific Integrated Chips). The model encompasses various automated techniques to identify logic within a given design which in turn can be leveraged for approximation. Following this identification the model uses a series of physical optimizations which lead to a tunable approximate circuit capable of operating in both approximate and accurate modes of operations depending on the environment and user constraints. The flow has been demonstrate to provide up to 35% power reduction in ASICs (operating in approximate mode) that implement imaging applications such as video decoding and image restoration IPs.

With increasing adoption of newer technologies and architectures targeted for automotive and aviation electronics with an objective to improve performance and/or reduce power/area, soft-error robustness is becoming an important issue to ensure reliable operation for an extended lifetime over a wide range of operating conditions. In this paper, we propose a modeling and optimization framework to systematically improve the FIT (failure-in-time) rate of a design with minimal impact on power, performance and area. We first propose a framework to model and evaluate the relative vulnerability to soft errors of the standard master-slave flip-flops and Dual Interlocked Storage Cells (DICE) in the cell library. Later, we formulate a linear optimization problem using this information to selectively replace the flip-flops so as to improve the FIT rate of the design with minimal impact on area and power. Employing the proposed technique on a popular industrial IP core shows a 32% relative improvement in the design robustness with just 2% increase in design area.

A hierarchical or "divide-and-conquer" scan test methodology enables us to partition a large SoC into several partitions and perform Design-for-Testability (DFT) functions such as scan insertion, pattern generation, and pattern validation separately on individual partitions. Since the effort for DFT related tasks grows super-linearly with gate count, partitioning reduces the effort for DFT tasks. Further, test application can be divided into k + 1 modes, where k modes correspond to independent testing of the partitions and the (k + l)th mode corresponds to a "residual" (or daisy) mode where faults that are not covered by the individual modes are considered. In reality, however, the daisy mode can be a killer and wipe out the benefits of divide-and-conquer testing. This is especially true for partitions that do not have test wrappers. In this paper, we take up the challenge of reducing the overhead of daisy mode in divide-and-conquer testing. By a careful analysis of the interactions between partitions, additional test modes are introduced to increase the coverage of glue logic, at the same time making sure that the number of scan cells involved in these "intermediate daisy modes" are minimal. We refer to this version of hierarchical scan testing as "Quiet and Optimized Divide-and-Conquer Scan". Experimental results reveal that the proposed technique reduces the test time overhead of the conventional daisy mode by about 20X. In addition, the technique drastically reduces the switching activity in the daisy modes and hence reduces the test power. © 2007 IEEE.

Excessive dynamic voltage drop in the power supply rails during test mode is known to result in false failures and impact yield when testing devices that use low-cost wire-bond packages. Identifying and debugging such test failures is a complex and effort-intensive process, especially when scan compression is involved. From a design cycle-time view point, it is best to avoid this problem by generating "power-safe" scan patterns. The generation of power-safe patterns must take into consideration the DFT architecture, physical design, timing and power constraints. In this paper, we propose such a framework and show experimental results on some benchmark circuits. Our framework can address a non-uniform power grid and region-based power constraints. We show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power. Our framework includes a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns. © 2007 IEEE.