Veezhinathan Kamakoti

Microfluidics is an upcoming field of science that is going to be used widely in many safety-critical applicationsincluding healthcare, medical research and defence. Hence, technologies for fault testing and fault diagnosis of these chips areof extreme importance. In this study, the authors propose a scalable pseudo-exhaustive testing and diagnosis methodology forflow-based microfluidic biochips. The proposed approach employs a divide-and-conquer based technique wherein, largearchitectures are split into smaller sub-architectures and each of these are tested and diagnosed independently.

System test and online test techniques are aggressively being used in today's SoCs for improved test quality and reliability (e.g., aging/soft-error robustness). With gaining popularity of vertical integration such as 2.5D and 3D, in the semiconductor industry, ensuring thermal safety of SoCs during these test modes poses a challenge. In this paper, we propose a dynamic test scheduling mechanism for system tests and/or online test that uses dynamic feedback from on-chip thermal sensors to control temperature during shift (or scan) and capture, thereby ensuring thermal-safe conditions while applying the test patterns. The proposed technique is a closed loop test application scheme that eliminates the need for separate thermal simulation of test patterns at design stage. The technique also enables granular field-level configuration of thermal limits, so that different units across multiple cores are subjected to customized thermal profiles. Results from implementation of the proposed schemes on a 4-layer, 16-core, 12.8 million gates, OpenSparc S1 processor subsystem are presented. Copyright © 2012 American Scientific Publishers. All rights reserved.

Conventional ATPG tools help in detecting only the equivalence class to which a fault belongs and not the fault itself. This paper presents PinPoint, a technique that further divides the equivalence class into smaller sets based on the capture power consumed by the circuit under test in the presence of different faults in it, thus aiding in narrowing down on the fault. Applying the technique on ITC benchmark circuits yielded significant improvement in diagnostic resolution. © 2013 IEEE.

Microfluidic biochips are widely accepted as the medical technology of the future. The reflection of this fact can be seen on the growth rate of the biochip industry as well. As these chips are used for many safety-critical applications, the testing and diagnosis of faults on them is of prime importance. In this paper, we present a simple approach for diagnosing faults on flow-based biochips using a two-stage search space pruning technique. The proposed technique employs a graph-theoretic bi-connected component based analysis which is much simpler and faster than those previously reported in the literature.

Excessive power dissipation can cause high voltage droop on the power grid, leading to timing failures. Since test power dissipation is typically higher than functional power, test peak power minimization becomes very important in order to avoid test induced timing failures. Test cubes for large designs are usually dominated by don't care bits, making X-leveraging algorithms promising for test power reduction. In this paper, we show that X-bit statistics can be used to reorder test vectors on scan based architectures realized using toggle-masking flip flops. Based on this, the paper also presents an algorithm namely balanced X-filling that when applied to ITC'99 circuits, reduced the peak capture power by 7.4% on the average and 40.3% in the best case. Additionally XStat improved the running time for Test Vector Ordering and X-filling phases compared to the best known techniques.

This paper demonstrates a trade off between the security of a crypto-system and its power consumption. Digital stream ciphers are extensively employed in Crypto-systems. Many of them use linear feedback shift registers (LFSRs) as building blocks, wherein, an n-degree primitive connection polynomial is used as a feedback function to realize an n-bit LFSR. Using finite-field theory and electromagnetic-circuit theory, we show that such LFSRs are susceptible to differential power attacks (DPAs), without the adversary's prior knowledge of the primitive polynomial. It is interesting to note that the DPA becomes more prominent with technology scaling due to increased contribution of local interconnect to total power. The paper also presents two countermeasures for the proposed DPA that results in a trade off with power consumption. With the growing need for crypto-systems in low-power Internet-of-Things (IoTs) devices, this case study highlighting a power-security trade off is of great significance.

IR-Drop induced timing failures during testing can be avoided by minimizing the peak capturepower. This paper models the Capture-Power minimization problem as an instance of the Bottleneck Traveling Salesman Path Problem (BTSPP). The solution for the BTSPP implies an ordering on the input test vectors, which when followed during testing minimizes the Peak Capture-Power. The paper also presents a methodology for estimating a lower bound on the peak capture-power. Applying the proposed technique on ITC'99 benchmarks yielded optimal (equal to the estimated lower bound) results for all circuits. Interestingly, the technique also significantly reduced the average power consumed during testing when compared with commercial state-of-the-art tools. Copyright © 2013 American Scientific Publishers All rights reserved.

Due to the increase in manufacturing/environmental uncertainties in the nanometer regime, testing digital chips under different operating conditions becomes mandatory. Traditionally, stuck-at tests were applied at slow speed to detect structural defects and transition fault tests were applied at-speed to detect delay defects. Recently, it was shown that certain cell-internal defects can only be detected using at-speed stuck-at testing. Stuck-at test patterns are power hungry, thereby causing excessive voltage droop on the power grid, delaying the test response, and finally leading to false delay failures on the tester. This motivates the need for peak power minimization during at-speed stuck-at testing. In this article, we use input toggle minimization as a means to minimize a circuit’s power dissipation during at-speed stuck-at testing under the Combinational State Preservation scan (CSP-scan) Design-For-Testability (DFT) scheme. For circuits whose test sets are dominated by don’t cares, this article maps the problem of optimal X-filling for peak input toggle minimization to a variant of the interval coloring problem and proposes a Dynamic Programming (DP) algorithm (DP-fill) for the same along with a theoretical proof for its optimality. For circuits whose test sets are not dominated by don’t cares, we propose a max scatter Hamiltonian path algorithm, which ensures that the ordering is done such that the don’t cares are evenly distributed in the final ordering of test cubes, thereby leading to better input toggle savings than DP-fill. The proposed algorithms, when experimented on ITC99 benchmarks, produced peak power savings of up to 48% over the best-known algorithms in literature. We have also pruned the solutions thus obtained using Greedy and Simulated Annealing strategies with iterative 1-bit neighborhood to validate our idea of optimal input toggle minimization as an effective technique for minimizing peak power dissipation during at-speed stuck-at testing.

Conventional manufacturing/system tests point to a set of logically equivalent faults and not the exact fault within a faulty component. In this paper, we show that during testing, measuring the current drawn by a faulty component aids in identifying the exact manifested fault within it. We propose to partition the chip's power grid based on the chip's component partitions, and dedicate a external supply pin to each component partition. In order to minimize the cost associated with the external measurement circuitry, we reuse the scan resources available within the flip-flop to repeatedly apply the desired test-pattern pair, so that the average current measured during the launch-to-capture window, is equal to the same over a long period of time. The proposed technique is validated by simulating the power-grid and the modified flip-flop using SPICE circuit simulator. The proposed technique, when applied to several component benchmark circuits, helped to localize almost all the logically equivalent faults.

In Digital ICs, energy consumed in scan test cycles is known to be higher than that consumed during functional cycles. Scan-cell reordering (SCR) is a popular technique to reduce test energy consumption. Conventional SCR techniques use the number of toggles in the scan flip-flops as cost criteria for reordering. The energy consumed during the scan test cycles includes that consumed by the logic and that consumed by the scan-chain. Interconnects contribute to more than 50% of the scan-chain energy consumption. Motivated by this, the paper proposes an SCR technique that uses the wire capacitances, in addition to the toggle criteria to perform the reordering. Results obtained by employing the technique on ISCAS89 benchmarks and OpenCores show a reduction in total scan-shift energy of up to 32% and a 11 × reduction in total scan-chain wire length. It is interesting to note that just applying the SCR without considering the interconnect capacitances may lead to increase in scan-chain energy consumption in some cases. Additionally, we observe that a significant portion of the total scan-shift power comes from the first-level capacitance, contributed by both interconnects and input capacitances of gates at the first level of logic. Using this, we show that first level capacitance gating, which gates this switching capacitances of the flop-logic interconnect and first-level gates during scan-shift saves power significantly over first-level supply gating. Combining the above two methods, when applied to ISCAS89 and OpenCores benchmark circuits, we get 62% total scan-shift energy savings with a delay penalty of 3%, on the average on the functional performance of the circuit, compared to the best known algorithm. Copyright © 2012 American Scientific Publishers All rights reserved.