Veezhinathan Kamakoti

This paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. The proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA. © 2005 IEEE.

This paper proposes a new CLB architecture for FPGAs and associated testing and reconfiguration techniques that detect single routing/interconnect errors and correct them using partial reconfiguration. The results of error detection are propagated to a single output port by a chain-like shift register, which are used to reduce the segment of the routing architecture that has to be reconfigured. The error is corrected by partially reconfiguring the above minimal segment alone, thereby reducing the time for reconfiguration. The proposed testing technique detects all possible routing errors that affects the logic of the circuit, including bridging faults. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA. Empirically, our technique detected all single interconnect errors in benchmark circuits. In addition, for the majority of errors, our correction technique required less than 10% of the switch matrices to be reconfigured to correct the errors.

This paper proposes a new reconfigurable system which has a function generator-based CLB architecture. This is different from the standard look-up table (LUT) based CLB architectures available in commercial FPGAs. The new function generation architecture is based on the fact that a small set of κ-input Boolean functions can generate all the 22κ, κ-input Boolean functions using a simple mapping technique. The area required by the new function generation architecture is 58,6% lesser than the area required by a standard 16 × 1 LUT used in commercial FPGAs. In addition, the proposed architecture consumes 40.8% lesser power than the standard 16 × 1 LUT. The routing architecture for the proposed reconfigurable system is the same as those present in current-day FPGAs. Hence, the algorithms presently used for technology mapping, packing, placement and routing on FPGAs can be used for the proposed reconfigurabie system without much modification. The new architecture requires a 10% in-crease in the SRAM configuration memory. This is an insignificant penalty in comparison to the reduction in the area of the FPGA and power consumption, achieved by the proposed CLB architecture. © 2005 IEEE.

This paper proposes a new CLB architecture for FPGAs and associated online testing and reconfiguration techniques that detect configuration upsets in the LUTs of SRAMbased FPGAs and correct them using partial reconfiguration. These configuration upsets may either be Single Event Upsets(SEUs) or even Multiple Configuration Upsets. Any error in a CLB is detected with a latency of just 16 clock cycles and the errors are diagnosed by propagating them to a single output port by a chain-like shift register. The proposed CLB architectures requires only 2 additional SRAM configuration bits per LUT for a Xilinx Virtex II architecture. This is extremely low when compared to the 16 additional SRAM configuration bits required by CLB architectures used to implement standard DWC techniques for detecting configuration upsets in LUTs.

This paper proposes a function-generation based area-aware Configurable Logic Block (CLB) architecture and an associated packing technique, for SRAM-based FPGAs. The new CLB architecture provides the same logic functionality, but occupies 38% less area, consumes 38.37% less power and requires 50% less configuration-bits per CLB when compared to the standard 4-LUT CLB architecture. The proposed packing technique is timing-driven and is shown to produce designs with almost same routing cost and performance overhead as that produced by the T- VPack algorithm on standard benchmark circuits. © 2006 IEEE.

This paper proposes a cluster-based parity-checking technique that can detect 100% of ail Single Event Upset (SEU) faults in the LUTs of SRAM-based FPGAs. The paper describes two different Configurable Logic Block (CLB) architectures that could be used to implement the proposed SEU detection technique. Of the two, the first architecture can perform at-speed testing of the LUTs without interrupting the normal functioning of the FPGA. The second one works by switching the CLBs from normal-mode to testing-mode and vice-versa. The LUTs are tested in the testing-mode. The switching frequency can be externally programmed and hence varied depending on the rate of SEU occurrences. Both the proposed architectures were compared with the Xilinx Virtex and Virtex Pro architecture. The proposed architectures require only 2 (when compared with Virtex) and 4 (when compared with Virtex Pro) additional SRAM configuration bits per LUT. This is extremely low when compared to the 16 additional SRAM configuration bits required by CLB architectures used to implement standard DWC techniques for detecting SEUs in LUTs. The area requirements of both the proposed architectures are also significantly less than the area requirements of DWC techniques. The proposed detection technique requires only 3 clock cycles of the Xilinx Virtex internal clock to detect the effect of an SEU in any LUT of the FPGA. © 2005 IEEE.

This paper proposes a new CLB architecture for FPGAs that can detect and correct Single Event Upset (SEU) faults in the LUTs. A methodology for mapping logical functions onto the LUTs is presented that exploits the features of the proposed CLB architecture to detect and correct the SEU faults in the LUTs. Experimental results obtained by mapping standard benchmark circuits on the proposed architecture indicate that on an average, 96% of the SEU in the LUTs can be detected without employing any redundancy. Further, by using Duplication with Comparison (DWC) techniques it is shown that 100% of the SEU in the LUTs can be detected for any circuit that is mapped on the proposed architecture; and for the benchmark circuits, on an average, 96% of the SEU in the LUTs can be automatically (without any user intervention or reconfiguration) corrected. © 2004 IEEE.