Veezhinathan Kamakoti

This paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. The proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA. © 2005 IEEE.

Deeply scaled CMOS circuits are vulnerable to soft and hard errors. These errors pose reliability concerns, especially for systems used in radiation-prone environments like space and nuclear applications. This paper presents SHAKTI-F, a RISC-V based SEE-tolerant micro-processor architecture that provides a solution to the reliability issues mentioned above. The proposed architecture uses error correcting codes (ECC) to tolerate errors in registers and memories, while it employs a combination of space and time redundancy based techniques to tolerate errors in the ALU. Two novel re-computation techniques for detecting errors for the addition/subtraction and multiplication modules are proposed. The scheme also identifies parts of the circuitry that need to be radiation hardened thus providing a total protection to SEEs. The proposed scheme provides fine-grain error detection capability that help in localization of the error to a specific functional unit and isolating the same, rather than the entire processor or a large module within a processor. This provides a graceful degradation and/or fail-safe shutdown capability to the processor. The HDL model of the processor was validated by simulating it with randomly induced SEEs. The proposed scheme adds an extra penalty of only 20% on the core area and 25% penalty on the performance when compared with conventional systems. This is very less when compared to the penalty incurred by employing schemes including double modular and triple modular redundancy. Interestingly, there is a 45% reduction in power consumption due to introduction of fault tolerance. The resulting system runs at 330M Hz on a 55nm technology node, which is sufficient for the class of applications these cores are utilized for.