Saurabh Saxena

A highly digital two-stage fractional- N phase-locked loop (PLL) architecture utilizing a first-order 1-bit ΔΣ frequency-to-digital converter (FDC) is proposed and implemented in a 65nm CMOS process. Performance of the first-order 1-bit ΔΣ FDC is improved by using a phase interpolator-based fractional divider that reduces phase quantizer input span and by using a multiplying delay-locked loop that increases its oversampling ratio. We also describe an analogy between a time-to-digital converter (TDC) and a ΔΣ FDC followed by an accumulator that allows us to leverage the TDC-based PLL analysis techniques to study the impact of ΔΣ FDC characteristics on ΔΣ FDC-based fractional- N PLL (FDCPLL) performance. Utilizing proposed techniques, a prototype PLL achieves 1 MHz bandwidth, -101.6 dBc/Hz in-band phase noise, and 1.22 ps rms (1 kHz-40 MHz) jitter while generating 5.031GHz output from 31.25MHz reference clock input. For the same output frequency, the stand-alone second-stage fractional- N FDCPLL achieves 1MHz bandwidth, -106.1dBc/Hz in-band phase noise, and 403 fs rms jitter with a 500MHz reference clock input. The two-stage PLL consumes 10.1mW power from a 1V supply, out of which 7.1 mW is consumed by the second-stage FDCPLL.