Qadeer Ahmad Khan

A Fully foldable modified Dickson architecture (FFMDA) based switched-capacitor dc-dc converter is proposed in this paper. The proposed converter uses only 4-stages in contrast to 5-stages in a regular Foldable Dickson converter to achieve the same number of gain settings, thereby becomes 20% area efficient. Peak efficiency improvement of 16% is achieved with a fully-foldable nature of proposed architecture in combination with subtraction mode. The converter is implemented in 130nm technology and uses stacked MOS and MIM capacitors to get the highest density. Operating at 2V input, the converter provides a wide range of regulated output voltages from 0.2 to 1.28V and delivers load current from 100µA to 2mA with average and peak efficiency of 71.35% and 87.5%, respectively.

This paper presents a capacitor-less low dropout (LDO) regulator that requires no frequency compensation, with the use of an adaptive-deadzone ring amplifier. Due to the dynamic behavior of the ring amplifier depending on the input voltage, the proposed LDO features a hybrid (digital or analog) operation and achieves both fast transient response and high output accuracy with a low quiescent current. Moreover, an adaptive deadzone biasing scheme is employed to ensure high stability for a wide range of load current operating conditions. A 1V LDO prototype with 80mA maximum load current is implemented in a 0.18?m CMOS process, consuming only a quiescent current of 6.5?A with a dropout voltage of 90mV. It achieves 172-432ns settling time for load current transitions between 1mA and 81mA. The active area is 0.1mm2.

This paper proposes an analog-assisted digital output capacitor-less low-drop out (LDO) regulator. At full load, the digital loop supplies greater than 90% of the load whereas the rest is supplied by the analog loop. The analog loop regulates the output accurately eliminating the limit cycle oscillations and quantization error due to a standalone digital LDO. The analog loop is implemented with a flipped source follower architecture to achieve lower output impedance and higher bandwidth.. The digital loop employs 32-bit shift register to control the discrete set of power-FETs. A fast clock (250 MHz) is used to speed up the digital loop during load transients and a slower clock (10 MHz) is used in steady state for power saving. The LDO uses only 1pF as output capacitor and consumes a quiescent current of 17.3µA. The proposed LDO was implemented in TSMC-65nm for an input of 1.2V, output of 1V and achieves settling time less than 110ns with undershoot/overshoot of 24mV/72mV for 0.1-10mA/100ns load step.

This tutorial discusses design of a highly integrated, low quiescent current continuous time PWM controller using time-based signal processing. By virtue of the continuous-Time digital nature of the time-based PWM controller, it is capable of achieving very high resolution and speed without using any error amplifier and large compensation capacitor or any high resolution A/D converter and digital PWM while preserving all the benefits of both analog and digital PWM controllers. Using time as the processing variable, the controller operates with CMOS-level digital-like signals but without adding any quantization error. A voltage/current controlled ring oscillator is used as an integrator in place of conventional opamp-RC or Gm-C integrator while a voltage/current controlled delay line is used to perform voltage-To-Time conversion. Starting with trade-offs with high speed design of conventional analog and digital PWM controllers, the concept of time based proportional-integral-derivative (PID) controller with complete architecture of a time-based buck converter is presented. The technique was successfully demonstrated on silicon with implementation of 10-25MHz single phase and 30-70MHz 4-phase buck converters on 180nm and 65nm CMOS processes, respectively.

This paper proposes a zero output ripple buck converter for low noise applications. Unlike the conventional zero ripple converter which requires perfectly matched inductors, the proposed converter uses a novel inductor mismatch compensation technique to achieve perfect ripple cancellation. In order to prevent the loop instability due to inversion of PWM signal in the ripple cancellation path, a split PWM controller is used. Implemented in 180nm CMOS process, the proposed converter achieves simulated output ripple of less than 300µV for the entire range of duty cycle (0 to 100%) with peak efficiency of 93.5% for the load current of 0.1-1A at 2.5MHz switching frequency. An undershoot/overshoot of 86mV/56mV with settling time of less than 3.5µS was achieved when a load step of 0.5A/50ns is applied at the output.

We present a supply supervisory circuit that makes use of an adaptively biased current comparator achieving fast response time (1.8 μ s) while consuming very low quiescent current (Iq). A Burst mode charge-pump is used to ensure monitoring down to 0.75V. This is the lowest reported common monitoring and operating supply for supervisory circuits. Fabricated in 130nm CMOS, this work achieves an Iq(nA) x Delay (μ s) FoM of 29, a 70x improvement over state-of-the-art supply supervisory circuits.

A time-based operational amplifier (OP-AMP) with high gain and a wide bandwidth is presented in this paper. The proposed OP-AMP utilizes voltage-controlled oscillator (VCO) as an ideal integrator to replace the conventional voltage-based error amplifier which provides infinite DC gain. The OP-AMP is compensated with a feed-forward Gm amplifier with capability of driving load capacitance up to 200pF. Proposed OP-AMP uses only 2pF of on-chip capacitor and consumes low quiescent current (70μA at typical corner and temperature). It further utilizes time-based offset cancellation technique to reduce the effect of mismatch between VCOs. The proposed OP-AMP was designed in TSMC 65nm CMOS LP process technology with input/output common mode voltages as 0.3V-0.7V and input power supply of 1.2V; achieving unity gain bandwidth (UGB) of 36MHz. A case study involving reference buffer for a 12-bit SAR ADC and a track and hold circuit are presented to demonstrate the versatility and performance of the proposed OP-AMP.

An output capacitor-less low-drop out (LDO) regulator using a feed-forward compensation is presented in this paper. The power stage; implemented using flipped-voltage-follower (FVF) stage along with the feed-forward compensation stabilizes the LDO for the entire range of load current and load capacitor. The LDO uses only 1pF of compensation capacitor and consumes quiescent current of 28µA in active mode and 3µA in low power (LP) mode. A load current sensor is used to sense ultra-low power and automatically switch to LP mode. The proposed LDO was implemented in TSMC-65nm for an input of 1.2 V, output of 0.9V to 1.1V and achieves settling time of <1µs with undershoot/overshoot of ~250mV for 10mA load current.

An output capacitor-less low drop-out (LDO) regulator using time-based error amplifier is presented in this paper. The proposed LDO utilizes voltage-controlled oscillator (VCO) as an integrator to replace the conventional voltage-based error amplifier. It reduces the overall area by using only 1.2pF of on-chip capacitor while consuming low quiescent current (<30μA at typical corner). Using time as the processing variable, the time-based error amplifier operates with full-swing CMOS digital like signals without introducing any quantization error. The proposed LDO was designed in TSMC 65nm CMOS LP technology with input and output voltages as 1.2 V and 0.8V-1.1V, respectively, achieving a regulation bandwidth of 3MHz. Settling time of 200ns or less was achieved for 10mA load current step and 0-100pF output load capacitor.

An ultra-low quiescent current capacitor-less low-drop out (LDO) regulator is proposed in this paper. The LDO is designed using domino control which automatically increases or decrease the drive strength based on load current. Quiescent current of the proposed LDO also varies with load current hence current consumption is minimized under light load condition. The proposed LDO architecture is fully scalable and can be easily scaled up for higher load currents with almost no design efforts. Implemented in TSMC-65nm, it uses only 1pF of on-chip compensation capacitor and consumes a quiescent current of 11.5µA. For an input of 1.2 V and output of 0.9V to 1.1V, settling time of <200ns with undershoot/overshoot of 62mV/40mV for 0-5mA in 100ns load step is achieved 1pF output capacitor.