Qadeer Ahmad Khan

A Fully foldable modified Dickson architecture (FFMDA) based switched-capacitor dc-dc converter is proposed in this paper. The proposed converter uses only 4-stages in contrast to 5-stages in a regular Foldable Dickson converter to achieve the same number of gain settings, thereby becomes 20% area efficient. Peak efficiency improvement of 16% is achieved with a fully-foldable nature of proposed architecture in combination with subtraction mode. The converter is implemented in 130nm technology and uses stacked MOS and MIM capacitors to get the highest density. Operating at 2V input, the converter provides a wide range of regulated output voltages from 0.2 to 1.28V and delivers load current from 100µA to 2mA with average and peak efficiency of 71.35% and 87.5%, respectively.

This paper proposes a zero output ripple buck converter for low noise applications. Unlike the conventional zero ripple converter which requires perfectly matched inductors, the proposed converter uses a novel inductor mismatch compensation technique to achieve perfect ripple cancellation. In order to prevent the loop instability due to inversion of PWM signal in the ripple cancellation path, a split PWM controller is used. Implemented in 180nm CMOS process, the proposed converter achieves simulated output ripple of less than 300µV for the entire range of duty cycle (0 to 100%) with peak efficiency of 93.5% for the load current of 0.1-1A at 2.5MHz switching frequency. An undershoot/overshoot of 86mV/56mV with settling time of less than 3.5µS was achieved when a load step of 0.5A/50ns is applied at the output.