Glitch-aware pattern generation and optimization framework for power-safe scan test

Excessive dynamic voltage drop in the power supply rails during test mode is known to result in false failures and impact yield when testing devices that use low-cost wire-bond packages. Identifying and debugging such test failures is a complex and effort-intensive process, especially when scan compression is involved. From a design cycle-time view point, it is best to avoid this problem by generating "power-safe" scan patterns. The generation of power-safe patterns must take into consideration the DFT architecture, physical design, timing and power constraints. In this paper, we propose such a framework and show experimental results on some benchmark circuits. Our framework can address a non-uniform power grid and region-based power constraints. We show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power. Our framework includes a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns. © 2007 IEEE.