Noise shaping techniques for SNR enhancement in SAR analog to digital converters

In principle, the resolution of a successive approximation (SAR) analog-to-digital converter (ADC) can be increased by 1 bit by quadrupling the area and the power dissipation. In practice, due to the increased size of the capacitor array and consequent higher mismatch, the resolution is limited to 12-13 bits. Calibration or trimming can be used to improve the resolution beyond this, but are expensive in area and test time. This work presents a 12-bit SAR ADC embedded in a first-order noise shaping loop to obtain a 16-bit resolution while maintaining sample-by-sample correspondence. Using a sub-quantization DAC in parallel with the LSB DAC allows the conversion cycles to be shorter than the first, increasing the effective sampling rate. Dynamic element matching is used in the 6-bit MSB DAC. The integrator in the loop filter is implemented with minimal overhead using one of the stages of the multistage preamplifier in the comparator. Measurements of a 0.6 µm prototype show 0.7 LSB INL and 0.3 LSB DNL at the 16-bit level and 92 dB peak SNDR for 2.5 kHz input at a 250 kS/s sampling rate.