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  1. Home
  2. Indian Institute of Technology Madras
  3. Publication12
  4. Parallel arithmetic expression evaluation on reconfigurable meshes
 
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Parallel arithmetic expression evaluation on reconfigurable meshes

Date Issued
01-01-1994
Author(s)
Pradeep, B.
C Siva Ram Murthy 
Indian Institute of Technology, Madras
DOI
10.1016/0096-0551(94)90008-6
Abstract
In this paper we present an O(log n) time parallel algorithm for arithmetic expression evaluation, on an n × n processor array with reconfigurable bus system, where n is the sum of the number of operators and constants in the expression. The basic technique involved here is leaves-cutting (rake operation), as in the case of PRAM model algorithms available in the literature for this problem. The input to our algorithm is assumed to be the binary tree associated with a given expression (also known as expression tree with n number of nodes). Our algorithm is faster compared to the previous best time for expression evaluation on mesh connected computers which is O(√n). © 1995.
Volume
20
Subjects
  • Expression evaluation...

  • Expression tree

  • Parallel algorithm

  • Rake operation

  • Reconfigurable mesh

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