Subthreshold CMOS Implementation of the Izhikevich Neuron Model

Neuromorphic computing seeks to build hardware systems that are similar to the brain in form and function. Such systems are composed of artificial neurons and synapses, both of which will have to operate with extreme energy efficiency to allow spiking neural networks to scale to the size of the brain. In this work, we present such a low-power subthreshold implementation of the Izhikevich neuron model, inspired by the circuit introduced by Wijekoon and Dudek. The circuit, designed in the UMC 65nm process, consumes 11.74fJ/spike at a 0.18V supply voltage, while operating on a biological timescale and allowing analog tunability of control voltages so as to exhibit different spiking behaviors. The circuit comprises an integrated digital spike transceiver that communicates with AER arbitration circuitry and generates reset pulses.