ASIC design of a matching unit for NLP

If natural language processing systems are to be practically useful, the response should be immediate, which implies faster processing. Preliminary studies on an ATN parser showed that a hardware accelerator for matching an input with the lexical entries will significantly improve system performance. In this paper, we report on the ASIC design of a matching unit. The logic verification and timing analysis of the matching unit were carried out using the Actel Viewlogic System, after which the FPGA devices were fused. An estimate of about a 20% to 30% improvement in system performance is projected. © 1995.