Delay-efficient bus encoding techniques

On-chip buses in deep-submicron designs have large propagation delay due to dominant coupling capacitance. As delay impacts system performance, several techniques have been proposed in the literature to minimize it. A common point in most of the existing techniques is to consider uniformly distributed random data, but propagation delay is data dependent and data is application dependent. Different applications may have different data behaviors. The existing techniques which consider uniformly distributed random data may not exploit the exact data behavior of an application and hence can give inferior performance results. By exploiting similarity in the data transmitted on on-chip buses, we propose three delay minimization techniques, namely, data packing (DPack), data permutation (DPerm), and data replication with shielding and two-phase transmission (RESTP). We show that for a 5-mm 32-bit on-chip bus in 90 nm CMOS technology, the DPack, DPerm, and RESTP techniques achieve more than 25%, 32%, and 51% delay savings, respectively, in both address and data buses. For a 32-bit bus, the DPack, DPerm, and RESTP techniques require 38, 34, and 48 wires, respectively. © 2009 Elsevier B.V. All rights reserved.