Publication: Samo: store aware memory optimizations
Date
01-01-2014
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Abstract
Cache optimizations and DRAM scheduling play an impor-tant role in determining the performance of a system given that the demand for memory is ever increasing. In this paper we track stores both at cache and main memory and apply three different optimizations, one, at the cache level, so that stores are serviced faster and hence load store queue block cycles are reduced, two, at the miss handling architecture wherein we remove entries containing only store requests thereby reducing the cache stall cycles and three, at the main memory where stores are serviced with lesser priority so that actual reads get serviced faster. These three differ-ent memory optimizations combined together (store aware memory optimization, SAMO framework) on an average in-crease the performance of the system and can be augmented with any previously proposed optimization techniques at the memory. SAMO speeds-up the workloads on 4-and 8-core sys-tems by a geometric mean of 5:0% and 7:4%, respectively, with a maximum speed-up of 21:9% and 17:8% on 4-and 8-core systems, respectively. © 2014 ACM.
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Keywords
DRAM scheduling, MSHR optimization, Store queue