A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth

We present a CTΔ Σ M which uses a virtual-ground-switched resistor DAC to achieve low distortion by reducing the effects of inter-symbol interference (ISI), and parasitic resistance in the reference path. 1/ f noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a 3-stage OTA, and an 8-tap FIR feedback DAC. Fabricated in 180nm CMOS, the prototype modulator operates at 32MS/s and achieves 103.5/107.5dB SNDR/DR in a 250kHz bandwidth while consuming 24mW. The Schreier FoM is 173.7dB.