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  1. Home
  2. Indian Institute of Technology Madras
  3. Publication10
  4. On-Line Location of Multiple Faults in LUT based Reconfigurable Systems
 
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On-Line Location of Multiple Faults in LUT based Reconfigurable Systems

Date Issued
01-12-2003
Author(s)
Kalyan Kumar, L.
Ramani, Aditya S.
Mupid, Amol J.
Veezhinathan Kamakoti 
Indian Institute of Technology, Madras
Suresh, S.
Abstract
This paper describes a novel on-line method for locating multiple faulty Lookup Tables (LUTs) in SRAM based reconfigurable systems. Earlier work was primarily concerned with single output LUT networks, which were fanout free and consisted of only one faulty LUT. The algorithm presented in the earlier works attempted to locate that single faulty LUT. Our method is designed for multiple fault location in general combinational LUT networks with multiple outputs and fanout. It uses the pseudo-exhaustive Built In Self-Test technique, which preserves the interconnect structure (in-place) of the LUT network. It involves selective reprogramming of LUTs and takes advantage of partial reconfiguration. Experimentally it is shown that this method provides good fault coverage in identifying faulty LUTs. Moreover, it is independent of the type and the number of faults within an LUT.
Subjects
  • Built-in Self Test

  • LUT-based FPGA system...

  • Multiple faults

  • Pseudo-Exhaustive Tes...

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