Implementation of a 30 ps resolution time to digital converter in FPGA

We present the design of a wide range and high resolution time to digital converter (TDC) on FPGA. The multiplexers present in the dedicated carry chain on the FPGA are used in the presented architecture to create the delay line for the conversion. The TDC has been implemented on Spartan-3E FPGA from Xilinx and a resolution of about 30 ps was achieved. The TDC was calibrated against test signals generated using the digital clock manager and varying lengths of wire to generate the controlled delays. With the high resolution TDC implemented, we have realized a wide range (coarse grain and fine grain) TDC and demonstrated the same by performing the jitter measurements for the applied input pulse.