Repository logo
  • English
  • Català
  • Čeština
  • Deutsch
  • Español
  • Français
  • Gàidhlig
  • Italiano
  • Latviešu
  • Magyar
  • Nederlands
  • Polski
  • Português
  • Português do Brasil
  • Suomi
  • Svenska
  • Türkçe
  • Қазақ
  • বাংলা
  • हिंदी
  • Ελληνικά
  • Yкраї́нська
  • Log In
    or
    New user? Click here to register.Have you forgotten your password?
Repository logo
  • Communities & Collections
  • Research Outputs
  • Fundings & Projects
  • People
  • Statistics
  • English
  • Català
  • Čeština
  • Deutsch
  • Español
  • Français
  • Gàidhlig
  • Italiano
  • Latviešu
  • Magyar
  • Nederlands
  • Polski
  • Português
  • Português do Brasil
  • Suomi
  • Svenska
  • Türkçe
  • Қазақ
  • বাংলা
  • हिंदी
  • Ελληνικά
  • Yкраї́нська
  • Log In
    or
    New user? Click here to register.Have you forgotten your password?
  1. Home
  2. Indian Institute of Technology Madras
  3. Publication5
  4. Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback
 
  • Details
Options

Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback

Date Issued
01-02-2018
Author(s)
Jain, Ankesh
Pavan, Shanthi
DOI
10.1109/TCSI.2017.2740287
Abstract
The use of a single-bit quantizer in a wideband CT Δ Σ M is attractive, as the quantizer can be implemented in a power and area-efficient manner. Unfortunately, 1-bit CT Δ Σ Ms are plagued by a host of difficulties. Clock jitter and quantizer metastability are particularly problematic, and the higher loop filter linearity needed to process the full-scale feedback waveform results in increased power dissipation. The use of a finite impulse response (FIR) feedback DAC is a power efficient way of addressing the challenges above. However, even this technique runs into difficulties at multi-GHz clock rates. This paper introduces the idea of time-interleaved (TI) FIR feedback to enhance the performance of a conventional FIR DAC. A single-bit CT Δ Σ M that uses a 2 × TI-FIR DAC achieves 67.6/68.8/76 dB SNDR/SNR/DR in a 60 MHz bandwidth. Designed in a low leakage 65 nm CMOS process, the modulator operates at 6 GHz and occupies only 0.07 mm2. Its Walden Figure of Merit is 56.5 fJ/lvl.
Volume
65
Subjects
  • distortion

  • FIR DAC

  • jitter

  • Oversampling

  • single-bit

Indian Institute of Technology Madras Knowledge Repository developed and maintained by the Library

Built with DSpace-CRIS software - Extension maintained and optimized by 4Science

  • Cookie settings
  • Privacy policy
  • End User Agreement
  • Send Feedback