Performance evaluation of High Bandwidth Memory for HPC Workloads

Recent advances in 3D integrated fabrication have allowed the development of 3D stacked memory. The technology presents itself as a viable solution to the memory wall problem. The 3D memory has stacked DRAM layers over the logic die connected through Through Silicon Vias (TSVs). In this paper, we study the performance of latency and energy of one such 3D stacked memory, namely the High Bandwidth Memory (HBM). We quantify the performance improvement of HBM2 against its predecessor technology, GDDR5, and competing mature technology, GDDR6. We have integrated the DRAMSim3 simulator with the Structural Simulation Toolkit simulator and have studied the High-Performance Computing Workloads from Rodinia Benchmarks Suite (RBS). In our paper, we carry out the evaluation of HBM2 and GDDR6 technology by varying the following metrics of the synthetic benchmarks- the number of instructions, and the read to write ratio. We observe the total execution time, memory cycles, and energy consumed for the RBS benchmarks. Our evaluation for synthetic benchmarks reveals that the read write latency performance of HBM2 is the orders of magnitude better than the GDDR6 technology. For real-world benchmarks, the execution time for HBM2 provides ∼ 30% improvement compared to GDDR6 and energy savings of ∼ 23% from GDDR6 to HBM2.