A 2-Channel 1 MHz BW, 80.5 dB DR ADC using a Delta Sigma Modulator and Zero-ISI Filter

It is shown that memoryless analog-to-digital conversion using Delta Sigma modulators is possible without resetting the modulator or decimation filters by using a suitable signal transfer function for the modulator and a decimation filter which satisfies Nyquist intersymbol interference (ISI) criterion. This architecture enables memoryless operation over the entire signal bandwidth of the Delta Sigma modulator which is significantly higher than the bandwidth in incremental Delta Sigma architectures in which the modulator is reset. A two-channel ADC with a total effective sampling rate of f(s)/64 per channel is built using a third order 32x oversampled switched-capacitor Delta Sigma modulator. The prototype in 0.18 mu m CMOS occupies 2.1 mm(2) and consumes 59.63 mW. At 16 MHz (64 MHz) sampling rate for the DSM, the dynamic range (DR) of the standalone modulator is 86.5 dB (85.1 dB), and that in two-channel mode, with perchannel rate of 250 kHz (1 MHz) is 81 dB (80.5 dB). The maximum SNR in multiplexed mode at 16 MHz (64 MHz) sampling rate is 803 dB (68.6 dB). At both sampling rates, the inter-channel crosstalk due to maximum input on the other channel is below 77.7 dB.