Shakti-T : A RISC-V processor with light weight security extensions

With increased usage of compute cores for sensitive appli-cations, including e-commerce, there is a need to provide additional hardware support for securing information from memory based attacks. This work presents a unified hard-ware framework for handling spatial and temporal mem-ory attacks. The paper integrates the proposed hardware framework with a RISC-V based micro-Architecture with an enhanced application binary interface that enables soft-ware layers to use these features to protect sensitive data. We demonstrate the effectiveness of the proposed scheme through practical case studies in addition to taking the de-sign through a VLSI CAD design ow. The proposed pro-cessor reduces the metadata storage overhead up to 4 x in comparison with the existing solutions, while incurring an area overhead of just 1914 LUTs and 2197 IP ops on an FPGA, without affecting the critical path delay of the pro-cessor.