Parallel implementation of 2D-Discrete Cosine Transform using EPLDs

A novel implementation of Two Dimensional Discrete Cosine Transform (2D-DCT) using Embedded Programmable Logic Devices (EPLDs) has been proposed in this paper. The key feature of this scheme is that it's architecture is regular, linear, pipelined and it fits into just four numbers of commercially available EPLDs. It is capable of processing images of size 512×512 pixels at rates of 25 frames per second. The chip set offers device independent design and can be used in conjunction with other processors. The algorithm implemented can be easily modified and remapped as per needs with a minimum of effort since the architecture is realized using modular Hardware Description Language (HDL). The hardware complexity and accuracy of the proposed DCT processor compare favourably with those of other known implementation techniques.