A 280 mu W Audio Continuous-time Delta Sigma Modulator with 103 dB DR and 102 dB A-Weighted SNR

An optimally designed FIR feedback DAC is used in a third order, single bit continuous-time delta sigma modulator to reduce power dissipation and jitter sensitivity. The loop filter is carefully stabilized for the delay added by the FIR DAC. A current reuse two stage feedforward compensated opamp minimizes current consumption in the first integrator. The efficacy of our techniques is borne out by measurements from a 17 bit audio converter designed in a 0.18 mu m CMOS technology. It achieves 103 dB dynamic range, 102 dB A-Weighted SNR and 106 dB SFDR in a 24 kHz bandwidth and dissipates 280 mu W from a 1.8V supply.