An area minimization technique for implementing pipelined IIR filters

Loop unfolding has been an important technique to implement high-speed HR digital filters. However, extra silicon area is required for implementing the FIR filter function that provides the 'cancelling-zeroes' in the unfolded IIR filter. We present IIR filter architectures that use pipelining and resource-sharing to overcome this drawback. Comparative results of standard-cell based implementation are presented. The new architecture shows a 1.6 times improvement of the sampling rate of a first-order IIR filter when compared to the normal implementation, while retaining the area-delay product.