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An area-efficient pipelined array architecture for Euclidean distance transformation and its FPGA implementation
Date Issued
24-05-2004
Author(s)
Sudha, N.
Abstract
The Euclidean Distance Transform (EDT) is an important tool in image analysis and machine vision. This paper provides an area-efficient hardware solution to the computation of EDT on a binary image. An O(n) hardware algorithm for computing EDT of an n × n image is presented. A pipelined 2-D array architecture for hardware implementation is designed. The architecture has a regular structure with locally connected identical processing elements. Further, pipelining reduces hardware resources. Results of FPGA-based implementation shows that the hardware can process about 6000 images of size 512 × 512 per second which is much higher than the video rate of 30 frames per second.
Volume
17