Publication: Gain enhanced high frequency OTA with on-chip tuned negative conductance load
Date
27-07-2015
Authors
Nagendra Krishnapura
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
An enhanced gain, high frequency, operational transconductance amplifier (OTA) architecture using negative conductance load to cancel its output parasitic conductance across process, voltage, and temperature (PVT) variations without the need of any off-chip intervention is proposed. Simulation results of a prototype transconductor in 0.13μm CMOS process over process corners, 100°C temperature range, and ±10% supply voltage variations show that the DC gain is enhanced from 14dB to 48dB when cancellation using negative conductance is incorporated. A minimum DC gain of 34dB and an average DC gain of 46dB is observed over 500 Monte-Carlo mismatch runs. The OTA has a unity gain bandwidth (UGB) of 20GHz.