SHAPER: Synthesis for hybrid FPGAs containing PLAs using reconvergence analysis

This paper discusses the technology mapping problem on Hybrid Field Programmable Architectures (HFPA). HFPAs are realized using a combination of Lookup Tables (LUTs) and Programmable Logic Arrays (PLAs). HFPAs provide the designers with the advantages of both LUT-based Field Programmable Gate Arrays(FPGA) and PLAs. Specifically, the use of PLAs leads to reduced area in mapping the given circuit. Designing of Technology mapping methodologies which map a given circuit on to the HFPA that exploits the above-mentioned advantages is a problem of great research and commercial interest. This paper presents SHAPER, which maps the circuits onto HFPAs using reconvergence analysis. Empirically, it is shown that SHAPER yields better area-reduction than the previous known algorithms. © 2004 IEEE.