Options
Log-sum multiplier
Date Issued
07-06-1976
Author(s)
Agrawal, J. P.
Reddy, V. U.
Abstract
A scheme for implementing a fast parallel multiplier based on a log-sum method is presented. The scheme for an n-bit by n-bit multiplication uses Q, least integer greater than or equal to (n2-n)/4, 4-bit Carry-Look-Ahead (CLA) adders. The worst case time for multiplying two sign + 12-bit numbers is estimated to be 180 ns when TTL 7400 series I.C.s are used. The scheme can easily be modified to use M-bit (M>4) CLA adders if and when available.