Synthesis of a control unit from instruction set specification in VHDL environment

Automated design of control structures for digital systems has been one of the active areas of research in high level synthesis. This paper proposes a methodology for specifying an instruction set in VHDL and also presents a system for synthesizing controller for the target processor. The goal of this system is to serve as a tool to help in early evaluation of instruction sets for implementation in a processor design environment. The system accepts the instruction set specification and a microarchitecture description and generates a finite state machine controller. A suitable subset of VHDL has been defined for easy specification of instruction set. Facilities have also been provided to define system timings and to specify clock synchronous activities of the processor. The output is given in VTI FSM compiler format for further processing to generate PLA or standard cell implementation of the controller.