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  1. Home
  2. Indian Institute of Technology Madras
  3. Publication10
  4. Performance enhancement in asymmetric gate dielectric MOSFET
 
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Performance enhancement in asymmetric gate dielectric MOSFET

Date Issued
01-12-2007
Author(s)
Havaldar, Dnyanesh S.
Katti, Guruprasad
Jadeja, B. M.
Rao, Rathnamala
Nandita DasGupta 
Indian Institute of Technology, Madras
Amitava Das Gupta 
Indian Institute of Technology, Madras
DOI
10.1109/ICM.2007.4497742
Abstract
The Asymmetric Gate Dielectric (AGD) MOSFET, where the equivalent dielectric thickness is higher at the source end than at the drain end, is studied with the help of simulations. A study of the properties of this device shows that, compared to the symmetric structure, the channel electric-field is larger at the source end resulting in higher carrier velocity and smaller at the drain end resulting in reduced short channel effects. The AGD devices show lesser Drain Induced Barrier Lowering and higher voltage gain compared to conventional devices, which should be useful for both digital and analog applications. The device structure has also been optimized for best performance. © 2007 IEEE.
Subjects
  • Drain Induced Barrier...

  • Gate dielectric

  • MOSFETs

  • Voltage gain

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