CASCADE: Congestion aware switchable cycle adaptive deflection router

Shrinking process technology poses a challenge to network-onchip design for high performance and energy efficient router architecture to interconnect multiple cores on a chip. Because of its importance, several router micro-architectures are proposed in the literature. In this paper, we propose a novel router architecture, congestion aware switchable cycle adaptive deflection (CASCADE) router, which dynamically reconfigures itself from single-cycle buffer-less router to two-cycle minimally-buffered router, and vice-versa, based on the router congestion level. The CASCADE router employs congestion aware cycle switching and power-gating to achieve both power and performance efficiency under varying network loads. Experimental results show that, when compared to SLIDER, the state of the artminimally buffered deflection router, theCASCADE router achieves on average 19% power reduction and 26% flit latency reduction with marginal area overhead.