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  1. Home
  2. Indian Institute of Technology Madras
  3. Publication11
  4. Silicon-on-insulator (SOI) wafer fabrication for MEMS applications
 
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Silicon-on-insulator (SOI) wafer fabrication for MEMS applications

Date Issued
01-12-2002
Author(s)
KotiReddy, Bhimanadhuni R.
Rao, P. R.S.
Amitava Das Gupta 
Indian Institute of Technology, Madras
Bhat, K. N.
Abstract
In this paper, it is shown that Silicon-On-insulator (SOI) wafers with good surface finish and thickness control can be realized using Silicon Fusion Bonding along with an optimized ethylenediamine-pyrocatechol-water (EDP) etching approach. Single crystal diaphragms of 11 μm thickness have been fabricated using these SOI wafers. These diaphragms were tested and found to withstand N2 gas pressures in excess of 260 psi without rupturing.
Volume
5062
Subjects
  • Diaphragm

  • EDP etching

  • Silicon Fusion Bondin...

  • SOI

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