Fast Hartley transform implementation on DSP chips

Of late, the fast Hartley transform (FHT) has attracted considerable research interest as an alternative tool to the fast Fourier transform (FFT). In this paper, efficient implementation of the FHT on different DSP processors is considered. Instead of counting the required arithmetic operations, the necessary number of instruction cycles for an implementation of FHT is used as a measure. Also, different scaling schemes, which are available in the literature, have been considered to increase the signal-to-noise ratio (SNR) of the algorithm. Finally, the details of the programs on ADSP2101, TMS320C25 and TMS320C30 have been presented.